數字鎖相環 的英文怎麼說

中文拼音 [shǔzìsuǒxiānghuán]
數字鎖相環 英文
digital phase locked loop
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 字 : Ⅰ名詞1 （文字） character; word 2 （字音） pronunciation 3 （字體） form of a written or printed ...
  • 鎖 : Ⅰ名詞1 （安在開合處使人不能隨便打開的器具） lock 2 （姓氏） a surname Ⅱ動詞1 （上鎖） lock up 2 ...
  • 相 : 相Ⅰ名詞1 （相貌; 外貌） looks; appearance 2 （坐、立等的姿態） bearing; posture 3 [物理學] （相位...
  • 環 : Ⅰ名詞1 （環子） ring; hoop 2 （環節） link 3 （姓氏） a surname Ⅱ動詞（圍繞） surround; encircle;...
  • 數字 : 1. （表示數目的文字; 表示數目的符號） figure; digit; numeral; character; numeric character 2. （數量） quantity; amount
  1. The results of experiment tell it is an effective method of share current. a strategy of synchronization control, which combines competition coequality and priority, is mentioned in the paper and uses digital phase - lock loop to track synchronization signal

    在同步控制上，應用了「優先與搶占」的方式產生同步信號，純硬體實現，簡單可靠；使用了成熟的數字鎖相環來跟蹤同步信號。
  2. Then we uses the scheme that has the variable gain based on the kalman filtering model realize two steps phase - locks ring circuit track technology, this kind has the advantage that when changed the gain the digital phase - lock link to be allowed simultaneously to realize the fast capture and the reliable track, the simulation analyzes its capture performance

    模擬結果表明，自編碼直擴通信系統的編碼捕獲性能具有可行性。採用基於卡爾曼濾波模型實現具有可變增益的二階鎖相環路的跟蹤技術，這種具有時變增益的數字鎖相環可以同時實現快速捕獲和可靠跟蹤，其捕獲性能要比傳統數字鎖相環改善很多。
  3. We design inversion control circuit with cmos figure pll cd4046 act as core and microprocessor 80c196kc act as assistant controller. adopting a control method that combine fuzzy controller and pll control, improve induction heating power succeed in startup. adopting electric current voltage pair closed loop feedback design, with trough route capacitance voltage and trough route electric current act as pair closed loop feedback signal, guarantee induction heating power output accuracy

    並對系統主電路的元器件參數進行了詳細的計算；設計了以cmos數字鎖相環cd4046為核心、以80c196kc作為輔助控制器的逆變控制電路；採用了模糊邏輯與鎖相環相結合的控制技術，提高了電源的啟動成功率；採用電流、電壓雙閉環反饋方案，採用槽路電容電壓和槽路電流作為反饋信號，從而保證了電源功率的輸出精度。
  4. The simulation results show the method can attain our aim under harmonic condition. then the calculation errors have been analyzed

    模擬結果表明，在有諧波干擾的情況下，數字鎖相環方法可以準確地跟蹤信號頻率的變化和計算相位差。
  5. According to the features of the signal of cmf, i. e. the signal frequency varies in a small range and the signal is subjected to the harmonics, a digital method based on a digital phase locked loop is used to process the signals of cmf, tracks the change of the signal frequency and calculates the phase difference. the technique proposed by the u. s. patent has been improved and made the simulation

    針對科里奧利質量流量計信號的特點，即信號頻率在小范圍內變化和信號易受諧波干擾的特點，採用基於數字鎖相環的方法處理科氏質量流量計的信號，跟蹤信號頻率的變化，計算相位差，對美國專利提出的方法進行了改進，並作了模擬。
  6. Research of adaptive spatio - temporal dfe with embedded dpll in high - speed underwater digital communication

    內嵌數字鎖相環的自適應空時聯合均衡器在水下高速數字通信中的應用研究
  7. The digital pll is of great importance in the control of the whole system

    第三章分析了調制器中所用到的數字鎖相環。
  8. Digital phase - locked loop

    數字鎖相環
  9. Based on the theory of dpll, line phase locked and color subcarrier regeneration were designed

    依據數字鎖相環的基本原理，完成了行鎖相、色副載波還原電路的設計。
  10. Digital phase lock loop is used in this section to synchronize to an incoming serial data stream

    數據接收解碼模塊中使用了數字鎖相環技術從輸入數據碼流中提取出同步時鐘信號。
  11. The digital phase - locked loop designed by isp, which is adapted to optical grating readout is briefly introduced

    用isp設計的適合於光柵檢測裝置的數字鎖相環在第七章作了簡要的介紹。
  12. 3. the dpll completed in software was advanced based on comparing the merits and disadvantages of analog pll with that of dpll. 4

    比較了模擬鎖相環和數字式鎖相環的優缺點，研究了一種基於軟體實現的數字鎖相環控制策略。
  13. Secondly the theory of phased - locked loop ( pll ) is analyzed in detail, and then a method of implementing digital phased - locked loop ( dpll ) is put forward. the algorithm is well implemented using digital signal processor ( dsp )

    然後對鎖相環原理進行了詳細的分析，提出一種數字鎖相環（ dpll ）的實現方法，並採用數字信號處理器（ dsp ）加以實現。
  14. In this paper, we are going to use high speed digital signal processor, track the carrier wave through the digital phase locked loop, and so to demodulate the modulating signal. it can overcome the difficult problems of the other ways

    而我們這里就是準備用高速數字信號處理器，利用數字鎖相環實現對載波的跟蹤，從而實現調制信號的解調，它能有效克服其他解調方式所遇到的困難。
  15. We design the digital phase - locked loop applying the method designing digital circuitry from the top down. we design the circuitry by the vhdl in the maxpulsii software environment. we validate the circuitry function in the emulator

    採用自頂向下的數字電路設計方法設計全數字鎖相環路，在maxplusii設計環境下採用vhdl語言、 ahdl語言等設計實現數字鎖相環，並通過計算機模擬證實其正確性。
  16. In the course of the design, critical technologies are applied, such as digital phase - locked loop, fast fourier transform algorithm, universal asynchronous receiver & transmitter, and so on. in the project, as a important component, the module of monitoring the buses " power quality takes a long time

    在設計過程中，使用的關鍵技術有：使用cpld模擬多路sspc多種狀態；在對匯流條電能質量的監測過程中採用頻率跟蹤技術? ?全數字鎖相環；應用fpga技術使用fft運算進行諧波分析；通用異步收發器等技術。
  17. The essential theory of analog phase lock loop ( apll ) and digital phase lock loop ( dpll ) are introduced

    然後介紹了模擬鎖相環和數字鎖相環技術，並對數字鎖相環的穩定性和穩態誤差性能進行了分析。
  18. Because of the structure of the traditional polarization diversity and combining scheme is too complex, after researching the polarization diversity and diversity combining technology, a new structure of receiver is proposed. in this structure the uniform sampling second - order dpll is used to remove the frequency bias after frequency discrimination

    該結構控制較為復雜，為此結合實際項目要求，在研究了極化分集接收關鍵技術的基礎上，提出了一種改進的極化分集接收機結構，即在鑒頻之後利用均勻采樣二階數字鎖相環誤差傳遞函數的高通特性去除各種頻偏分量。
  19. An idea is brought forth to design the total structure of the usb interface ip, the main control logic, the mcu interface ( the function is the same as the pdiusbd12 chip of the philips semiconductor ) and a dpll which is used to synchronize data and separate the clock. this paper also introduces packet recognition, transaction sequencing, sop, eop, reset, resume signal detection / generation, nrzi data encoding / decoding and bit - stuffing, crc generation and checking ( token and data ), packet id ( pid ) generation and checking / decoding,

    提出設計了usb介面電路的整體構架，設計了usb的主要控制邏輯和與mcu的互連的介面（此介面與飛利普的usb介面晶元pdiusbd12兼容） ，也設計了一個數字鎖相環（ dpll ）來同步數據和分離時鐘，並對同步模式的識別、并行/串列轉換、位填充/解除填充、 crc校驗/產生、 pid校驗/產生、地址識別和握手評估/產生做了具體的分析。
  20. And then the stability and the stable error response of the dpll are analyzed. there is an obvious doppler shift frequency offset in the received signal with flight at a high speed, in the dissertation the uniform sampling second - order dpll is used to remove the frequency bias for its excellent high - pass characteristic of the error transfer function

    由於高速飛行的遙測目標在接收信號中會出現較大的多普勒頻率分量，而典型均勻采樣二階數字鎖相環dpll （ digitalphase - lockedloop ）的誤差函數具有高通特性，所以本文提出一種利用其高通特性來去除多普勒頻率分量的新方法。
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