數碼總線 的英文怎麼說

中文拼音 [shǔmǎzǒngxiàn]
數碼總線 英文
number bus
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 總 : Ⅰ動詞（總括; 匯集） assemble; gather; put together; sum up Ⅱ形容詞1 （全部的; 全面的） general; o...
  • 線 : 名詞1 （用絲、棉、金屬等製成的細長的東西） thread; string; wire 2 [數學] （一個點任意移動所構成的...
  • 數碼 : numerical code; digit; figure
  1. One of the highest total connectivity rating in the region based on a cumulative penetration rate of main lines, mobile subscribers, integrated services digital network isdn subscribers and community antenna television catv and digital subscriber line accounts

    就主要電話線路行動電話用戶綜合業務數字網路isdn用戶有線電視和數碼用戶線路dsl帳戶的累計滲透率而言，香港是區內電訊總容量最大的地方之一
  2. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  3. Jx5 is a complex microprocessor, which contains cache, microcode rom, instruction prefetch unit, instruction decode unit, integer unit, mmx unit, floating point unit, page unit, bus unit, dp logic, apic and so on. it is very difficulty to test a such complicated microprocessor and receive anticipative fault coverage ratio. so, we must add dft in cpu ’ design

    Jx5微處理器是一款結構異常復雜的微處理器，它的內部包含有: cache 、微碼rom 、指令預取部件和動態分支預測部件、指令譯碼部件、整數部件、多媒體部件、浮點部件、分段和分頁部件、總線介面部件、雙處理器介面部件、可編程中斷控制部件等。
  4. The main content is design of digital man - machine interface system, a speed regulating system of good stabilization and dynamic performance ; software for appraising the performance of wire feeder. the first, a digital man - machine interface system using at89s8252 singlechip is designed. the system uses sd7218a keyboard / display chip with serial bus interface

    首先，人機交互系統選用at89s8252為核心控制晶元，選用具有串列總線介面的sd7218a鍵盤/顯示晶元完成了數字化人機交互系統軟、硬體設計;採用rs - 485總線實現主控系統和人機交互系統的數據交互;系統採用數字編碼器和鍵盤配合的方式實現焊接參數的選擇和設定，同時還具有最優參數存儲、調用等功能。
  5. Intelligence control system

    智能i2c數碼總線控制系統
  6. Although there have been many application instances in the field of input / output device technology, we need an specific project and technology route aimed at an given application. in this thesis, we combine the introduction and analysis of relative technology to describe the accomplishment of a coordinate collecting device which is based on incremental rotary encoder. this device is an specific device applied to collect the corrdinate displacement of ground image ’ s three - dimensional model created by full digital photogrammetric station. cpld chip and vhdl are applied in this device to carry out the following work : phase control of the electrical pulse created by incremental rotary encoder, counting the number of electrical pulse, controling the state of signal processing circuit, exchanging data between this circuit and pci control

    本文結合相關技術的介紹和分析，描述了一個基於增量式旋轉編碼器的坐標參量採集介面卡的實現，此介面卡是一種用於採集全數字攝影測量系統地面影像模型坐標位移量的專用設備，該設備採用cpld器件和vhdl語言實現增量式旋轉編碼器的脈沖信號鑒相和計數、信號處理部分的狀態控制以及和pci總線晶元ch365之間的數據交換和通信功能，同時該設備的驅動程序基於wdm模式，並且配置有結構良好的動態鏈接庫程序作為系統軟體和驅動程序之間的數據和控制交互中間介面，能夠方便地運行在windows98 / 2000 / xp操作系統平臺上，具有實時性強、工作穩定、通用性較好和性價比高等特點。
  7. According to the request of this subject, we have developed the system hardware and software for the slave device and the inspection software running on the pc. in this paper all of the followings is illustrated detailedly, such as the research on the principles of measurement and its realization, three means of water - level measurement that are separately based on photo electricity coder, pressure sensor and potentiometer ; selection of the microchip, we choose an advanced integrated soc ( system on chip ) microchip c8051f021 as the main controller ; realization of signal sampling, processing and its conversion in the mcu ; application of high precision 16 bits adc cmos chip - - ad7705 in our system, designing its interface with the microchip and relevant program ; using a trickle charge timekeeping chip ds1302 in the system which can provide time norm and designing of its i / o interface and program ; additionally, a 4 ~ 20ma current output channel to provide system check - up using ad421. in the system, ad421, ad7705 and the microchip compose spi bus ; to communicate with the master pc, here we use two ways which are separately rs232 and rs485 ; moreover, there are alarm unit, keyboard unit, power supply inspection unit and voltage norm providing unit in the system

    針對研製任務的要求，課題期間研製了下位機系統硬體和軟體，開發了上位機監控軟體，其中所作的具體工作包括：測量原理的研究和在系統中的實現，在本次設計中用三種方法來進行水位測量，分別是旋轉編碼器法、液位壓力傳感器法和可變電阻器法；主控晶元的選擇，我們選用了高集成度的混合信號系統級晶元c8051f021 ；實現了信號的採集和處理，包括信號的轉換和在單片機內的運算；高集成度16位模數轉換晶元ad7705在系統中的應用，我們完成了它與單片機的介面設計及程序編制任務；精確時鐘晶元ds1302在系統中的應用，在此，我們實現了用單片機的i o口與ds1302的連接和在軟體中對時序的模擬，該晶元的應用給整臺儀器提供了時間基準，方便了儀器的使用；另外，針對研製任務的要求，還給系統加上了一路4 20ma模擬信號電流環的輸出電路來提供系統監測，該部分的實現是通過採用ad421晶元來完成的，本設計中完成了ad421與單片機的spi介面任務，協調了它與ad7705晶元和單片機共同構成的spi總線系統的關系，並完成了程序設計；與上位機的通信介面設計，該部分通過兩種方法實現： rs232通信方式和rs485通信方式；系統設計方面還包括報警電路設計、操作鍵盤設計、電源監控電路設計、電壓基準電路的設計。
  8. During the design of vxi - bus serial controller module, the functions of vxi - bus including time - sequence for vxi interface, resource management, interrupt process, bus arbitration, are accomplished. to advance the performance and stability, the fpga technic is used to implement the kerneled code including serial bus time - sequence switching to vxi interface time - sequence, the uart, the parameterized baud generator and “ pipeling frame ”. the handle type of data transfer bus for vxi - bus is researched thoroughly, and the format of serial data transfer is designed

    在vxi總線串列控制器設計中，實現了vxi總線控制器的基本功能，包括vxi總線介面時序、總線仲裁、超時處理等;同時利用先進的fpga技術實現了串列總線時序向vxi總線時序的轉換、通用異步收發器（ uart ） 、參數化波特率發生器、流水線結構等功能模塊;在設計中還深入研究了vxi總線數據傳輸的各種操作類型，制定了串列數據傳輸的編碼格式。
  9. The main subject including : the constructure of this mpeg2 encoder ; ~ the principle and the system of tv, also the determination of tv signal ? pcm parameter and the international standard of video pcm ; ? he protocol of pci and the driver of pci device ; the hardware & software design of some corresponding interfaces of mpeg2 encoder, allowing for the working condition, there is some discussing on programming of mater control ; debugging and testing

    主要內容包括： mpeg2編碼器的體系結構；電視原理、制式以及電視信號的pcm編碼參數的選擇和pcm編碼的國際標準； pci總線協議標準及pci設備驅動程序的編寫； mpeg2編碼器的相關介面的具體硬體設計和相應的軟體設計，結合具體情況，討論了主控編程；硬體調試。
  10. This card largely depends on three integrate chips to fulfill its function : 1 ) nic control main chip, corresponding the mac sublayer of ethernet, to realize csma / cd media access protocol, manage the sending and receiving buffers integrated on the chip and provide motherboard pci interface. 2 ) serdes ( serializing and deserializing ) chip, corresponding pcs and pma sublayers in ethernet, mainly to complete 8b / 10b coding and convert 10 bits parallel data to serial data, and convert them again at the receiving end. 3 ) fibre transceiver unit, completing light - electrical conversion of seri

    該網卡主要由3塊集成的晶元完成其功能，分別是i ）網路控制主晶元，對應于以太網的mac子層，主要完成csmaicd介質訪問協議，管理片上集成的發送和接收緩沖區，並提供和主板p0總線的介面： b ） s rd s （串列解串列化器）晶元，對應于以太同的pcs和pma子層，主要完成sb lob編碼並將10位并行的數據轉換為串列數據，在接收端完成相反的功能：涌）光纖收發器，完成串列數據的光電轉換功能。
  11. The card is a independent instrument which can do white - black video image digitization, eompresing, coding and transmit the compressed image data to host computer by rs - 485 bus, so the card can solve the bottle - neck problem of the video supervise system completely

    該壓縮卡是一個獨立的視頻圖像壓縮和傳輸設備，它能直接對黑白電視信號進行數字化和壓縮編碼，並通過rs - 485總線將壓縮的圖象數據發送到上位機，徹底解決了視頻監控中的傳輸「瓶頸」問題。
  12. In addition, sarft has offered digital tv carriers in second and third tier cities exemptions from sales tax as an incentive

    廣電總局亦已向二三線城市的數碼網路營運商提供銷售稅減免，以鼓勵政策的推行。
  13. Mvb is an advanced bus used to control fix devices in trains, which uses reliable manchester coding and crc check coding ; and supplies more two type of data according to different time - critical needs. and mvb supplies every device with the communication interface and communication service

    其中多功能車輛總線mvb是目前最為先進的車輛內部設備控制總線，它的數據處理過程包括曼徹斯特編碼和crc校驗，並根據實際的應用要求能提供不同的數據支持，能為在總線上的各個設備提供通訊介面和通訊服務。
  14. Concretely, on the basis of describing the communication specification of arinc 429 with enhanced parallel port ( epp ), the standard and the module application of dsp and cpld, the thesis has proposed the design of the arinc 429 technology based on dsp system. at first, the function and the application of each module of the system and the operation principle of high - performance cmos bus interface circuit hs - 3282 chip which forms the main body of the data diversion of the interface module are introduced. secondly, the hardware structure of the interface module is described in detail, mainly including data latch and buffer circuit, choice circuit of transmission rate, etc. and then the design philosophy and flow charts of the software are fully discussed, such as the basic requirement of software, the design and realization of the function

    本文在簡單的論述了pc並口協議（ epp ）與dsp之間的通信方法、 cpld模塊邏輯控制應用和arinc429的通訊規范的基礎上，給出了基於dsp的arinc429通訊介面的設計方案:對通訊板中各模塊的功能和應用以及構成數據轉換主體的總線介面晶元hs - 3282的工作原理做了說明;介紹了本設計所用的dsp和cpld的功能概況;詳細敘述了通訊板介面模塊的硬體結構設計，其中，對數據緩沖電路、數據傳輸速率選擇電路、邏輯控制電路等各關鍵點做了重點介紹;具體闡述了軟體設計思想及流程圖，包括軟體的基本要求和功能的設計與實現;接著從埠譯碼單元、 i / o通道、電平轉換電路等方面進行了介面模塊的軟、硬體調試;最後，給出了測試結果，對研製工作做了總結，對本設計的優缺點各做了評述。
  15. The software controls the signal generator, which makes the brightness can be tracked. the software also controls the 12c bus interface. by setting the lcd tv ' s decoder, the software adjusts the white balance of the lcd tv

    白平衡系統的軟體控制白場信號發生器使得亮度可以自動跟蹤，軟體對cm - 7l送來的數據進行計算處理，並且根據處理的結果對i ~ 2c總線操作，修改液晶電視機內部解碼晶元中的數據達到白平衡調整的目的。
  16. The card is based on the flat roof of pc machine, at first, we are used of the source of program data to leave in ide care, then binary file is come by the send out card, which is transmitted the standard ' s transmission stream. according to the european the standard of dvb - c, variable transmission current velocity rate is 9. 6 - 38. 4 mbits / s

    此卡基於pc機平臺，首先將節目源數據以二進制文件的格式存放在普通ide硬盤上，然後通過計算機的pci總線將二進制文件經過發送卡轉換成符合數字電視asi （異步串列介面）介面標準的平穩碼流。根據歐洲dvb - c標準，可變的傳送流速率為9 . 6 ~ 38 . 4mbit s 。
  17. Based on the above analysis results, the system design is finished. the system design principal is detailed. the system architecture and data transmission proctocal are discussed. in order to transmit multi - channel data simutaneously on the monacable, tdm ( time division multiplexing ) technique is adoped in the system design. a special code is designed for data transmission on the tool - bus, so that the too - bus can both supply power and transmit data

    包括單芯電纜數據傳輸系統的設計思想、結構設計和數據傳輸協議的制定。在單芯電纜數據傳輸系統設計中，採用時分多路復用技術，實現多種參數儀器數據的同時傳輸。在儀器總線上採用特殊的碼進行數據傳輸，使得儀器總線既能供電又能傳輸數據。
  18. Embracing advanced digital radio communication and mobile computing technologies, cciii is the mission - critical system that hkpf relies on to support the 999 emergency services in the three regional command and control centres rcccs

    Cciii對警隊的運作十分重要，系統運用了先進的數碼無線電通訊和流動電腦技術，以支持三個總區指揮及控制中心的九九九緊急服務。
  19. Collaboration between the two branches was epitomised by the ongoing design and development of the third generation command and control communications system ( cciii ), which will be rolled out in three phases between late 2004 and early 2006. embracing advanced digital radio communication and mobile computing technologies, cciii is the mission - critical system that the force relies upon to support the 999 emergency services in the three regional command and control centres

    資訊應用科和通訊科合作的最佳例子，是第三代指揮及控制通訊系統（簡稱cciii ） 。這個系統將由二四年年底至二六年年初分三個階段推出。 cciii採用先進的數碼無線電通訊及流動電腦技術，以支援警隊三個總區指揮及控制中心的999緊急服務，是警隊的關鍵資訊系統。
  20. The system controlling logic, multiplexing data bus and multiplexing address bus have been designed. the simulations have passed

    完成了系統的控制邏輯、數據總線復用和解碼部分的地址復用器的設計，模擬並通過。
分享友人
分享到 Line

分享到臉書