時鐘同步器 的英文怎麼說

中文拼音 [shízhōngtóngbùqì]
時鐘同步器 英文
clock synchronizer
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 步 : Ⅰ名詞1 （步度; 腳步） pace; step 2 （階段） stage; step 3 （地步; 境地） condition; situation; st...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  1. In a synchronous counter all stages are triggered by a common clock.

    在同步計算器中，所有觸發器均由同一個時鐘觸發。
  2. It can reduce 30 minutes from 4 hours worktime by applying underslung and drawer - lide design reducing on internal channel of the stove and preheater

    錫爐內槽及預熱器均採用同步「懸臂抽屜設計」 ，保養工時由原長達4小時，縮短為30分鐘。
  3. The field of video signal processing is now undergoing a digital reform. the digital processing technique is clearly expatiated in this paper, such as a / d convert, anti - alias filter, clamp control, gain control, pll, synchronization circuit, color decoder, comb filters

    本文詳細敘述了視頻圖像的數字處理方法，重點介紹了視頻信號數字化技術、抗混疊濾波器、箝位、增益控制、鎖相技術、同步時鐘產生、電視信號亮色分離、彩色解碼等技術，這些關鍵技術為視頻信號的數字化處理提供了重要的基礎。
  4. The concept of " timing " in the article is not the clock in our ordinary living, but syntheses which is made up of some frequency source in the signal generator ( such as cs atom frequency standard, rb clock & high accuracy quartz crystal oscillator ) which produces the primary frequency, the matching input interface and the matching output interface and controlling circuit etc. for example, bits is a kind of timing equipment, which is used to control the timing of some functions

    本文論及的「時鐘」概念不是指日常生活中使用的鐘表，而是由產生基準頻率的信號發生器（如銫原子頻率標準、銣鐘及高精度石英晶體振蕩器等）中的某種頻率源以及相配套的輸入、輸出介面和控制電路等組成的一整套具有特定同步定時功能的綜合體。如bits就是一種時鐘設備，它提供用在通信系統中控制某些功能的定時的時間基準設備，時鐘提供的信號稱為基準信號、定時信號或同步信號。
  5. Contains information about checking job status, changing target servers for jobs, synchronizing target server clocks, and polling master servers for their current job status

    包含有關檢查作業狀態、更改作業的目標服務器、同步目標服務器時鐘以及輪詢主服務器以獲取當前作業狀態的信息。
  6. That is to say, the test system can be connected easily with other systems and be installded with the setup softwares by using socket communication. what is more, the scheme that the thesis mentioned just uses adapted ieee1588 to synchronize the collection machines ? network nodes, because there is no need to implement the whole ieee1588 in the simple enviroment, and an extend manner to implement the whole protocol is discussed in the master / slave communication

    本文對飛機測試系統外總線進行綜合分析后，並在理解了ieee1588的時鐘同步原理的基礎上，對ieee1588進行了裁減，並將裁減后的ieee1588協議應用到各數據採集器的同步策略中，使各採集器之間能達到精確的時間同步，進一步提出了在主/從方式的測試系統中實現完整ieee1588的擴充同步方案。
  7. The serializer and deserializer moduls in the ftlvds chip are designed by the way of standard cell design approach. the paper emphatically discusses the tradeoff and the implementation of several clock synchronization modes and circuit structures, and makes a lot of verilog simulation and verification on the circuits designed

    串並模塊串列化器和解串列器採用標準單元的方法設計，論文討論了對幾種時鐘同步模式以及串並轉換電路結構的權衡和實現，並對所設計的電路結構進行了verilog模擬驗證。
  8. To synchronize all target server clocks with the master server clock

    使所有目標服務器時鐘與主服務器時鐘同步。
  9. However, we noticed that many consumer pcs had internal clocks with a different speed, leading to desynchronization

    但是，我們注意到一些機器的內部時鐘速度不一樣，這樣會導致錯誤的同步。
  10. Qe1 achieve the whole synchronization by software and hardware. during the course of the initialization of the qe1 system, the chip pm4354 can accomplish the task of synchronization of bit, frame and multiframe after the chip initialization by the software. after pm4354 accomplishes the bit synchronization, qel will read the status registers of the pm4354 to get the status of each el circuit and choose recovered clock of the specified the el circuit as the external timing source of the whole htc - 5200an equipment

    Qe1系統在系統初始化時，通過軟體完成對硬體晶元pm4354的初始化工作后，便可利用該晶元完成4路e1的同步（位同步、幀同步和復幀同步） ；在pm4354完成時鐘提取的任務后， qe1通過不斷地訪問pm4354的狀態寄存器，獲得每路e1的狀態信息，在時鐘源的選擇原則下，選擇指定e1線路的恢復時鐘作為整個htc - 5200an節點設備的外部參考時鐘，從而解決了htc 5200an的中繼板卡由e1變為qe時所帶來的網同步時鐘源。
  11. In this thesis, the principle of polarized light wave transmit in optical fiber is researched, i. e. principle of ternary optical fiber communication is researched. based on the researches, the construction of ternary codes optical end machine and 3b2t optical end machine used in two - state fiber net are designed. the construction and component of circuits in 3b2t optical ( called sign converter circuit - scc ) are designed particularly, including : the clock synchronization module, the data synchronizing, code converting module, frame managing module and error exam and managing module

    本文研究了線偏光波動理論以及在光纖中的傳輸原理，研究了三值光通信系統原理和器件原理；在此基礎上，設計了三值光端機和在現有兩值光纖網中實現三值光通信的3b2t三值光端機的組成結構，詳細設計了3b2t三值光端機的電路組成部分（稱為電信號變換電路scc ） ，包括：時鐘同步模塊、數據同步模塊、碼元變換模塊、幀處理模塊及差錯檢測和處理模塊；而且在三值光纖通信基礎上，提出了四值光通信的原理和偏分復用的實用化方法。
  12. After power switch opening, the clock displayer display asynchronous timing information, so synchronous indicating lamp glimmer, when equipment receiving above four effective satellite information and getting synchronous, which synchronous indicating lamp blank off

    電源開關打開后，時鐘顯示器顯示未同步的時間信息，同步指示燈閃爍，裝置接受到四顆以上的有效衛星信息，並取得同步后，則同步指示燈熄滅。
  13. To synchronize your pc clock with the hong kong observatory s network time server, please follow the steps below

    若要將你的電腦時鐘與天文臺的時間伺服器同步校對，請按照以下步驟進行:在
  14. 2. using the method of dds + pll to generate the system clock and count clock which are synchronous. 3

    2 .通過dds + pll的方法實現脈沖/數據發生器所需的系統時鐘以及計數時鐘的產生，以及其同步的實現。
  15. The third row of the table represents synchronous parallel loading of the register and states that if s1 and s0 are both high, then, without regard to the serial input, the data entered at a is at output qa, data entered at b is at qb, and so forth, following a low - to - high clock transition

    表2中第三行表示計數器的同步平行的加載，和表明如果s1和s0為高電平，那麼它就不是連續輸入，在時鐘由低向高跳變后，在a端的數據輸入則在qa端輸出，在b端的數據輸入將在qb端輸出，等等。
  16. A design method based on the decomposition and multiplexing technique of complex instruction, combined the decoding arithmetic of instruction and a step counter together, sub - step realization method of multiclocks is proposed. the similarities and differences of architecture between fsm and multi - ? ocks are discussed from two aspects, timing and state space

    提出了執行周期復用的指令分解、指令寄存器與步長計數器聯合譯碼，以及多時鐘同步的控制流設計方法；進而從時間和狀態空間兩個角度深入討論了控制流設計中狀態機和多時鐘兩種常見體系結構的異同。
  17. Second, this dissertation implements separately a mpeg - 2 video decoder and a dolby ac - 3 digital audio decoder based on software mode, and gives a audio & video synchronization algorithm based on audio - clock - benchmark in mpeg - 2 system decoder, whose feasibility and practicability have been proved by experimenting. it is an all - purpose algorithm, which can perform different decoder according to mpeg - 1 or mpeg - 2 system models, and can also be used for reference to the implementation of other multiplex stream decoders

    然後，論文實現了基於軟體方式的mpeg - 2標準視頻及ac - 3格式壓縮音頻的實時解碼與回放，並依據mpeg - 2系統解碼模型實現了一種基於音頻基準時鐘的mpeg解碼器的視音頻同步演算法，實驗證明該演算法可行、實用、通用性好，對符合mpeg - 1或mpeg - 2系統標準的視音頻解碼器均具適用性。
  18. Then, memory cell array and some parts of peripheral circuits used in sram, for example, sense amplifyier and adderss decoder, are designed and verifyied by simulation. furthermore, some novel methods, such as clocked hierarchical word decoding structure, multi - stage sense amplifyier, common data line and data bus equlibruim technology has been applied in the design of 128kbit and imbit sram. what ' s more, we have studied compiler technology applied in the designing course of a imbit full cmos sram from the pointview of methology

    然後對sram的存儲單元電路以及外圍電路中的靈敏放大器和地址譯碼器進行了設計和模擬，在此基礎上，以128kb和1mb全cmossram設計為例，從方法學角度對同步sram設計中的帶時鐘分等級字線譯碼，多級靈敏放大和位線及總線平衡等技術進行了研究，並給出了相應的compiler演算法。
  19. The functional module and the mainboard compose an automatic measurement instrumentation with real - time data acquisition and processing function. this module involves two multi - channel adc and the sample clock is shared between these adc so as to synchronization

    本模塊使用了單片集成多通道同步a d轉換器，並在轉換器之間共享采樣時鐘的方法在模塊內部實現了通道間同步。
  20. Analyzing every part ’ s function and characteristic, i improve overflow control unit ’ s design technique to suit fpga design and traditional register exchange survivor managing algorithm. the system use input clock as system clock and use parallel structure in system to provide flexible speed

    採用適合fpga特點的溢出控制設計方法;改進傳統的寄存器交換法re （ registerexchange ）的倖存路徑管理設計方法;全系統採用輸入數據的同步時鐘作為系統時鐘，系統內部採用全并行的方式，以提供靈活的速度。
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