機電譯碼器 的英文怎麼說

中文拼音 [jīdiànyìmǎqì]
機電譯碼器 英文
electromechanical encoder
  • 機 : machineengine
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 譯 : 動詞（翻譯） translate; interpret
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 機電 : electromechanical機電設備 electromechanical equipment; electromechanical device
  1. In the part, there are following contents : single - chip and memory circuit, interrupt control circuit, decoding circuit, parameter area circuit, watchdog circuit and serial communication interface circuit, etc. in this paper, serial communication interfaces between upper pc and lower single - chips are designed

    其中，微處理器的設計是關鍵。在微處理器部分的設計中，主要包括以下內容：單片機及存儲器電路設計、譯碼器電路設計、參數區電路設計、中斷控制電路設計、看門狗電路設計、串列通信介面電路設計等。
  2. It has been playing an important role in equipping all kinds of arms and services for campaigns, tactical exercises and emergent actions etc. based on the detailed analysis of the exchange ' s architecture and implementing, this thesis points out some disadvantages of the device, such as too many absolute components, not very high enough reliability and security, very large size and weight, operating and maintaining difficultly. considering low power requirement and man - machine interface optimizing design at the same time, the thesis come up with an integrated design scheme to the previous device based on " mcu + cpld / fpga architecture " : ( 1 ) signal frequency dividing, timing frequency producing, 20 customers " led states controlling are implemented in cpld ; ( 2 ) decoding, latching data and controlling signals are implemented in cpld by bus interface between mcu and cpld ; ( 3 ) chip selecting principles and mcu idle mode design are completed under the consideration of low power requirement ; ( 4 ) operation by chinese lcd menus is adopted in the man - machine interface

    本項目以該交換機為研究對象，在詳細分析原設備的系統結構和功能實現方式的基礎上，指出該機型在使用過程中存在技術相對陳舊、分立元件過多、可靠性和保密性不夠、體積大、重量大、維修困難等問題，同時結合系統的低功耗需求和優化人機介面設計，本文提出基於「單片機+ cpld fpga體系結構」的集成化設計方案：在cpld中實現信號音分頻和計時頻率生成電路、 20路用戶led狀態控制電路； cpld與單片機以總線介面方式實現譯碼、數據和控制信號鎖存功能的vhdl設計；基於低功耗設計的器件選型方案和單片機待機模式設計；人機介面的lcd菜單操作方式。
  3. Audio codec requirements for the provision of bi - directional audio service over cable television networks using cable modem

    使用電纜數據機通過有線電視網路提供雙向音頻服務的音頻編碼譯碼器要求
  4. The circuit design mainly includes interface designs, such as address coding circuit, memory, human - machine, ad converter, the power, etc. the pcb was protracted and tested

    電路設計主要包括譯碼電路設計、存儲器介面電路設計、人機介面電路設計、 ad轉換器電路設計、數控恆流源介面設計等。
  5. The hardware system includes power supply circuit, clock reset circuit, jtag model building circuit, decoding circuit, memory interface circuit, man - machine interface circuit and numeric control constant - current source interface circuit

    硬體系統主要包括電源電路、時鐘復位電路、 jtag模擬介面電路，譯碼電路、存儲器介面電路、人機介面電路、 adc轉換電路和數控恆流源介面等。
  6. After a great amount of detailed computer simulations and concise qualitative and quantitative theoretical analysis, the turbo codes " parameters and fpga specific hardware implementation architecture suitable for being integrated into dtv systems are determined. furthermore, the codec is completely designed with verilog hdl, ending with an occupation of less than a 600 - thousand - gate fpga chip. at this lowest hardware cost, a white noise snr threshold of 1. 8db at a net stream rate of 6mbps is achieved, which exceeds all other existent dtv systems " performance

    經過大量詳細的計算機軟體模擬和簡明扼要的定性與定量的理論分析，最終確定了數字電視系統中適合採用的turbo碼參數及針對fpga特殊構架的硬體實現結構，並用verilog硬體描述語言完成了turbo碼編譯碼器的完整設計，以佔用不到一片60萬門fpga晶元的較少的硬體資源取得了在6mbps凈碼率下1 . 8db的白噪聲信噪比門限這一遠遠超過現有任何數字電視系統的性能。
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