浮點加 的英文怎麼說

中文拼音 [fúdiǎnjiā]
浮點加 英文
floating add
  • 浮 : Ⅰ動詞1 （漂在液體表面） float; drift 2 [方言] （在水裡游） swim Ⅱ形容詞1 （在表面上的） superfici...
  • 點 : Ⅰ名詞1 （液體的小滴） drop （of liquid） 2 （細小的痕跡） spot; dot; speck 3 （漢字的筆畫「、」）...
  • 浮點 : [計算機] floating decimal; floating point
  1. Vol. 121 of the ima volumes in mathematics and its applications, springer - verlag, berlin heidelberg, 2000, pp. 59 - 82. 9 murray j d. mathematical biology ii : spatial models and biomedical applications. 3rd edition, springer verlag, january 2003, pp. 141 - 191

    這樣，在存儲四個浮點數后，旋轉計算時，只需要12次加法和12次乘法將四元組轉為矩陣，並對一個頂點只進行6次加法和9次乘法。
  2. 2 montoye r k, hokenek e, runyon s l. design of the ibm risc system 6000 floating - point execution unit. ibm journal of research and development, 1990, 34 : 59 - 71. 3 oberman s. floating - point arithmetic unit including an efficient close data path

    我們採用90納米cmos標準單元工藝以及synopsys自動布局布線流程進行實驗，實驗結果表明該演算法在高性能雙通路結構的浮點加減運算中引入后，可以使得近路徑的運算延遲整體降低10 . 2 % ，且演算法本身沒有造成新的關鍵路徑。
  3. In this paper, a lot of researches and exploration are applied to studying the universality and expansibility of hardware and the arithmetic design and code optimization of software. especially, all of the following arithmetics or conceptions are worked out in the research of software design : self - adaptable compression arithmetic based on dictionary model for data collection system, similarity full binary sort tree, a optimized quick search arithmetic and an improved arithmetic of multiplication in the floating - point operation. and all of the arithmetic are designed with mcs - 51 assembly language. the quick search arithmetic, in which merits of both binary search and sequence search are used fully, are based on the specialty of preorder traversal in similarity full binary sort tree

    特別在軟體設計研究中，提出了適用於數據採集系統的數據壓縮演算法? ?基於字典模型的自適應壓縮演算法；提出了類滿二叉排序樹的定義；提出了基於類滿二叉排序樹的先序遍歷特性的最優化快速查找演算法，它充分利用了折半查找和順序查找各自的優點；提出了浮點運算乘法的改進演算法；並在mcs - 51匯編語言層次上對所有的演算法加以實現。
  4. This paper studies fpu ' s algorithm, data - path, control - path, and implements the integration of the powerpc603e system. this thesis mainly discusses the algorithms and the implementation of the floating point unit in the embedded powerpc603e microrpocessor

    論文的研究工作包括： ?研究浮點演算法，主要包括加減法、乘法、除法、開平方以及cordic （ coordinaterotationdigitalcomputer ）演算法。
  5. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  6. The data and conclusions prove that these designs are better than the original ones ; the floating - point adder is really optimized

    實驗證明這些設計的性能都比原有設計有所提高，達到了優化浮點加法器的目的。
  7. The main research area is the structure optimization of floating - point adder, which is intent to minimize the delay of floating - point addition and optimize the circuit structure

    主要研究方向是優化浮點加法器結構，減小浮點加法運算的延遲，優化電路結構。
  8. The algorithm and its implementation of the leading zero anticipation are very vital for the performance of a high - speed floating - point adder in today s state of art microprocessor design. unfortunately, in predicting " shift amount " by a conventional lza design, the result could be off by one position. this paper presents a novel parallel error detection algorithm for a general - case lza

    目前國際上已有很多演算法對前導0預測演算法進行了研究，但是出於設計方法和延遲等方面的限制，大部分前導0預測演算法都為非精確演算法，其預測結果可能與真實加法結果中前導0的個數產生一位的誤差，這個誤差需要在浮點加法的后規格化過程中進行修正，因此反過來又增加了浮點加減演算法的關鍵路徑延遲。
  9. After that, it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler. moreover, this paper explores the method of design the floating - point arithmetic unit. referring to the ieee754 - 1985 standard for binary floating - point arithmetic, the algorithm and the behavior description of floating - point adder and multiplier is given, and the simulation and verification is shown at the end of this paper

    此外，本文還對處理器的浮點運算單元設計做了初步的研究，以ansi ieee - 754浮點數二進制標準為參考，借鑒了經典的定點加法器和乘法器的設計，嘗試性的給出了浮點加法單元和乘法單元的實現模型和行為級上的硬體描述，並對其進行模擬和驗證。
  10. This article deals with the method to determine the guard digit in the left normatlization of float point number in the analysis and design of computer system, and briefly introduces its application in practice

    摘要介紹了在計算機系統分析和設計中，用於浮點數左規格化的警戒位的設置方法，並簡要說明了該類警戒位與用於舍入的警戒位共同組成了運算器中的累加器的實際警戒位字長。
  11. On the one hand it is important for the design of floating - point processor unit to optimize speed while algorithms of high - speed are introduced. for examples, two - path of high - speed floating - point addition, booth coding of floating - point multiplication. srt of floating - point division and square root, cordic of transcendental function and so on

    一方面浮點處理部件設計重點在於速度的優化，所以採用優化的高速演算法，如浮點加法的two - path 、浮點乘法的booth編碼、浮點除法和平方根的srt演算法以及超越函數的cordic演算法等。
  12. To compare two floating - point variables

    ）比較兩個浮點變量時應多加小心。
  13. The author is absorbed in research on technology of coprocessor design. in the floating - point addition the paper proposes a carry chain of dynamic and static mixed circuits and a good balance between speed and area of predicting leading - zero logic circuits, considering algorithm and construction of logic circuits. an approach of micro program controller design for coprocessor is put forward and a test bench is given to verify its function

    筆者研究協處理器的設計技術，在浮點加法器中提出動態與靜態結合設計進位鏈的方案以及前導零預測面積與速度的折衷方法；在微程序控制器的設計中提出一種協處理器微程序控制器的設計方法，並且給出其功能驗證的測試平臺。
  14. Any floating - point operation like addition or multiplication is achieved in a few discrete steps

    任何浮點操作，例如加法和乘法，都可以通過幾個步驟來實現：
  15. 1 schmookler m s, nowka k j. leading zero anticipation and detection - a comparison of methods. in proc. 15th ieee symposium on computer arithmetic, vail, co, usa, june 11 - 13, 2001, pp. 7 - 12

    該前導0預測糾正演算法對于尾數和為正數或者負數的情況下都能正確工作，因此不需要事先判斷尾數大小和進行尾數交換，適合在基於雙通路結構的高性能浮點加減運算中採用。
  16. And so on. as you can see, for a six - step floating - point addition, the speedup factor will be very close to six times at start and end, not all six stages are active as all stages are active at any given instant shown in red in figure 2

    正如您可以看到的一樣，對於一個6級的浮點加運算來說，加速比非常接近於6 （在開始和結束時，這六個步驟並不是都處于活動狀態的） ，因為在任何給定的時刻（圖2所示的紅色） ，這些步驟都是活動的。
  17. 26th ieee asilomar conference on signals, systems, and computers, pacific grove, ca, usa, october 26 - 28, 1992, pp. 391 - 395. 14 oklobdzija v. an algorithmic and novel design of a leading zero detector circuit : comparison with logic synthesis. ieee transactions on vlsi systems, 1993, 2 : 124 - 128

    而另一方面，該演算法與目前國際上其它類似演算法相比具有面積和功耗上的明顯優勢，根據實驗結果，採用該演算法所實現的電路面積比採用以往類似演算法所實現的電路面積減少了27 ，功耗則降低了28 ，因此特別適合在高性能低功耗的浮點加減運算演算法中採用。
  18. The proposed approach enables parallel execution of conventional lza and its error detection, so that the error - indication signal can be generated earlier in the stage of normalization, thus reducing the critical path and improving overall performance. the circuit implementation of this algorithm also shows its advantages of area and power compared with other previous work

    本文提出了一種新型的基於錯誤糾正機制的前導0預測演算法，該演算法在傳統非精確演算法的基礎上增加了對其結果出錯時的預判機制和規格化過程中的實時糾正機制，從而實現了尾數和規格化時的精確移位，降低了浮點加減運算的關鍵路徑延遲。
  19. The product rule is very simple and easy to implement, and it does n ' t increase additional delay

    該「產生式規則」簡單而易以實現，而且不增加浮點加法器的延遲。
  20. The primary contents and innovations of this article are introduced below. in order to take advantage of the high speed of calculation, and at the same time, improve the accuracy and dynamic - range of the algorithm, three kinds of multi - input floating point adder algorithm ( fpa ) are summarized and a high - performance multi - input fpa structure is put forward with a self - defined floating point format. the performance of the high - performance structure on calculation speed and logic resource consuming is better than the normal structure

    論文的主要工作及創新點如下:為了充分利用fpga處理速度快的特點，同時盡量提高演算法的精度及動態范圍，本文在對浮點加法器演算法進行深入研究的基礎上，規納總結了三種不同的多輸入浮點加法器演算法，並創造性地提出了一種高效的多輸入浮點加法器結構及一種適合於fpga實現的自定義浮點數格式，這種高效的結構在所需的邏輯資源和運算速度上均遠優于傳統的多輸入結構。
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