浮點數處理器 的英文怎麼說

中文拼音 [fúdiǎnshǔchǔlǐqì]
浮點數處理器 英文
fpu
  • 浮 : Ⅰ動詞1 （漂在液體表面） float; drift 2 [方言] （在水裡游） swim Ⅱ形容詞1 （在表面上的） superfici...
  • 點 : Ⅰ名詞1 （液體的小滴） drop （of liquid） 2 （細小的痕跡） spot; dot; speck 3 （漢字的筆畫「、」）...
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 處 : 處名詞1 （地方） place 2 （方面; 某一點） part; point 3 （機關或機關里一個部門） department; offi...
  • 理 : Ⅰ名詞1 （物質組織的條紋） texture; grain （in wood skin etc ） 2 （道理;事理） reason; logic; tru...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 點數 : check the number （of pieces etc ）; count; points; tally點數單 tally sheet; 點數單據 tallying do...
  1. Firstly, the dissertation expatiate the develop of epu ' s software and hardware. the hardware is a data acquisition system based on the ps multiprocessor architecture

    硬體是以主從式多處理器結構為核心數據採集系統，主機和從機分別採用ti公司浮點dsp晶元7ms320c31pq和定點dsp晶元tms320f240 。
  2. Jx5 is a complex microprocessor, which contains cache, microcode rom, instruction prefetch unit, instruction decode unit, integer unit, mmx unit, floating point unit, page unit, bus unit, dp logic, apic and so on. it is very difficulty to test a such complicated microprocessor and receive anticipative fault coverage ratio. so, we must add dft in cpu ’ design

    Jx5微處理器是一款結構異常復雜的微處理器，它的內部包含有: cache 、微碼rom 、指令預取部件和動態分支預測部件、指令譯碼部件、整數部件、多媒體部件、浮點部件、分段和分頁部件、總線介面部件、雙處理器介面部件、可編程中斷控制部件等。
  3. There are five parts in powerpc603e ? microprocessor : integer execution unit, floating point unit ( fpu ), instruction ( data ) cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way

    Powerpc603e微處理器系統由定點執行單元、浮點單元、指令（數據） cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令。
  4. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  5. After that, it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler. moreover, this paper explores the method of design the floating - point arithmetic unit. referring to the ieee754 - 1985 standard for binary floating - point arithmetic, the algorithm and the behavior description of floating - point adder and multiplier is given, and the simulation and verification is shown at the end of this paper

    此外，本文還對處理器的浮點運算單元設計做了初步的研究，以ansi ieee - 754浮點數二進制標準為參考，借鑒了經典的定點加法器和乘法器的設計，嘗試性的給出了浮點加法單元和乘法單元的實現模型和行為級上的硬體描述，並對其進行模擬和驗證。
  6. A processor usually has two sets of general - purpose registers, one optimized for floating - point operations and the other for integer operations

    一個處理器通常有兩組通用寄存器，一組優化為用於浮點運算，一組優化為用於整數運算。
  7. It cost about 313, 000, and in terms of price - performace ratio, this placed the avalon significantly above the 64 processor origin 2000 from silicon graphics, which produced the same crop of gigaflops for a cost of approximately 1. 8 million

    它價值大約31萬3千美元，並且在價格性能比方面，它排在silicon graphics的origin 2000 64位處理器之上，後者有相同數量的gigaflop （每秒十億次浮點運算）而價值大約180萬美元。
  8. Functions were added to allow access to and control of the floating point control word on both the x87 and sse2 floating point processor

    函數，以允許對x87和sse2浮點處理器上的浮點控制字的進行訪問和控制。
  9. Amex86 microprocessor is composed of integer processing unit, float - point processor unit ( math coprocessor ) and protect test unit

    Amex86系統由一個整數處理部件（ cpu ） 、一個浮點處理部件（數學協處理器）和一個保護測試單元組成。
  10. The primary contents and innovations of this article are introduced below. in order to take advantage of the high speed of calculation, and at the same time, improve the accuracy and dynamic - range of the algorithm, three kinds of multi - input floating point adder algorithm ( fpa ) are summarized and a high - performance multi - input fpa structure is put forward with a self - defined floating point format. the performance of the high - performance structure on calculation speed and logic resource consuming is better than the normal structure

    論文的主要工作及創新點如下:為了充分利用fpga處理速度快的特點，同時盡量提高演算法的精度及動態范圍，本文在對浮點加法器演算法進行深入研究的基礎上，規納總結了三種不同的多輸入浮點加法器演算法，並創造性地提出了一種高效的多輸入浮點加法器結構及一種適合於fpga實現的自定義浮點數格式，這種高效的結構在所需的邏輯資源和運算速度上均遠優于傳統的多輸入結構。
  11. Double is the most efficient data type, because the processors on current platforms perform floating - point operations in double precision

    是最有效的數據類型，因為當前平臺上的處理器以雙精度形式執行浮點運算。
  12. Double is the most efficient of the fractional data types, because the processors on current platforms perform floating - point operations in double precision

    是小數數據類型中效率最高的，因為目前各平臺的處理器都是以雙精度來進行浮點運算。
  13. The instrument can sample by dual channel simultaneously, and it can process float point data in high speed and high capacity. you can operate the instrument conveniently. data acquisition, storage, display, and analysis can be achieved on the spot

    該儀器可進行雙通道同步采樣，具有高速浮點數處理能力，容量大，操作簡單，功能強大，可完成對振動信號的採集、存儲、顯示和分析。
  14. More calculation already having an huge memory size, all controllers could now manage up memory words and could use double words and floatting point ( with more than 45 new instructions arithmeticc, trigonometric, conversion, . . )

    在已有的大內存容量基礎上，現在的twido控制器可以支持更多的內部字，雙字處理，以及浮點運算；並新增多達45種數學指令，包括算術運算、三角函數轉換等。
  15. In the project, the microprocessor is composed of integer unit and floating - point unit

    本課題所設計的微處理器共包括兩部分：整數單元和浮點單元。
  16. To decrease the area of the chip, resource sharing, which is a synthesized optimized method of eda tools, was used in the project. the code was verified in fpga soft ware environment. synthesized netlists based on fpga and asic were given in the paper for future work

    本課題所設計的微處理器的整數單元和浮點單元均採用硬體描述語言vhdl進行建模，為降低晶元面積，將資源共享這一eda工具的綜合優化方法應用於設計中，並在現有條件下進行了簡單的fpga驗證，考慮到今後的asic設計，本文給出了基於fpga和基於asic的兩種綜合網表。
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