硬體邏輯模擬 的英文怎麼說

中文拼音 [yìngtǐluómónǐ]
硬體邏輯模擬 英文
hardware logic simulation
  • 硬 : 形容詞1 （堅硬） hard; stiff; tough 2 （剛強; 堅定; 強硬） strong; firm; tough; obstinate 3 （勉...
  • 體 : 體構詞成分。
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 模 : 模名詞1. （模子） mould; pattern; matrix 2. （姓氏） a surname
  • 擬 : 動詞1. （設計; 起草） draw up; draft 2. （打算; 想要） intend; plan 3. （模仿） imitate
  • 硬體 : hardware
  • 邏輯 : logic
  • 模擬 : imitate; simulate; analog; analogy; imitation; simulation模擬艙 boilerplate; 模擬電路 [電學] circ...
  1. Finaiiy, the paper also has introduced the virtua1 worid of windows rs ; j { ? # - - lase / and how to map the 1ogica1 address to physica1 address in protected mode and the interrupt mechanism of protected mode, then the paper has i11ustrated that it is necessary to write virtua1 device driver ( vxd ) in order to access hardware device from the third leve1

    最後，在介紹了windows的虛擬世界，和在保護模式下如何將邏輯地址映射成物理地址，以及保護模式下的中斷機制的基礎上，闡明了在保護模式下應用程序對硬體設備操作驅動程序的必需的中間橋梁作用。
  2. In the hardware design, the paper completes modules ’ design like outside memory, patulous a / d, patulous d / a, rs232 communication, ecan communication, led control, keyboard control, distant control, emulation, reset, logic voltage switch, dsp supply power regulate and ac - dc power circuit, as well as room layout design like anterior panel, back panel etc. and dsp transfers data with peripheral equipments except outside memory using serial ports. besides, the whole circuit is configured in interrupt response. thus, it can meet system demand as well as take full advantage of tms320f2812 ’ s hardware resource. in the software design, the paper finishs programs like the interface programms intercommunicates with people, the distant control program, ad and da modules ’ control program, in addition, the paper select the velocity and acceleration state - feedback algorithm and is written in the program. the software design uses dsp integrate exploiting environment named ccs2. 2 of ti inc. as software instrument, and programs with the combination of c language and assembly language. moreover, in order to maintenance or modify the software expediently and shorten software ’ s exploitation time, the design adopt software modularization technique. finally, some air cylinder experiments are carried out to proved that the pneumatic controller is very practical

    在硬體設計中，本文完成了片外存儲器擴展、 a / d擴展、 d / a擴展、 rs232通信介面、 ecan通信總線介面、液晶顯示控制、鍵盤控制、遠程控制、模擬、復位、邏輯電平轉換、 dsp工作電源校正電路和ac - dc電源等模塊設計以及控制器前面板、後面板等的空間布局設計。其中dsp與除外部存儲器的外圍設備之間的數據傳送全部採用串口通信，同時系統電路配置成中斷響應方式，這樣既滿足了系統要求，又充分利用了tms320f2812的硬體資源。在軟體設計中，本文完成了人機界面功能模塊、遠程控制模塊、 ad擴展模塊、 da擴展模塊、速度和加速度狀態反饋的控制演算法的程序設計。
  3. By thorough analysis and synthetize this paper made a frame of the system of intelligent instrument and its hardware structure. as followed, this paper depicted design details of intelligent instrument " s hardware, it included the design of interface circuit, data commutations and digital logic of dsp, mcu, internet ' s chip and isp ' s apparatus etc., and have designed schematic map and circuit. so it accomplished the full design of hardware / software of the new type intelligent instrument

    本文具體給出了新型智能儀器硬體結構及實現，描述了智能儀器硬體設計細節，包括數字信號處理器、單片機、 internet接入晶元、可編程數字/模擬器件等在新型智能儀器中的介面電路設計、數據通信設計和數字邏輯設計等，詳細地給出了設計原理圖和電路圖；給出了新型智能儀器的軟體設計細節，從而完成了新型智能儀器完整的軟硬體設計。
  4. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  5. The hardware has two input channels of high - speed analog signal, with the signal amplitude of 0 - 5v, the conversion precision of 12bits, and the maximum sampling rate of 400ksps. this system includes 4 dsps ( adsp 2181 ), which can be arranged as a pipe line processing array. many algorithms can be realized in this system

    系統硬體有兩路模擬數據採集通道，模擬信號輸入范圍為0 ? 5v ，轉換精度為12位，最高采樣率400ksps ；系統包含4片dsp （ adsp2181 ）構成的流水線型的處理陣列，可用於實現各種演算法；系統的控制邏輯由fpga完成。
  6. The results of simulation prove that the improved algorithms are feasible for evolving the digital combinational logic circuits and improve the evolvable efficiency and convergence performance

    模擬實驗結果證明了改進演化演算法對于實現函數級數字組合邏輯電路的硬體演化是可行的，並且提高了演化演算法的演化效率和收斂性能。
  7. The hardware in this system includes a digital signal processor, an analogy input channel, a lcd, an analogy output path, a keyboard input part, a guard circuit and a logic control circuit

    該系統硬體包括數字信號處理器晶元、前向輸入通道、液晶顯示器、模擬量輸出部分、鍵盤輸入部分、保護電路部分和邏輯控制部分。
  8. This design for mvbc system adopts top - down eda common design flow. circuit design adopts veriloghdl coding description. function simulation and timing verification adopt simulation tool vcs of synopsys inc, the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc, and the fpga advice stratix ii ep2s15

    該mvbc系統設計採用業界通用的自上而下的eda設計方法，電路邏輯實現採用veriloghdl硬體語言描述，功能和時序驗證的動態模擬採用synopsys公司的vcs ，而邏輯綜合與fpga實現採用altera公司的集成開發環境quartusii軟體以及stratixiiep2s15的fpga器件。
  9. Including dsp ' s program under tl " s ccs environment, cpld ' s logic program under max + plus ii environment, system program under visual c + + and so on

    根據本系統硬體邏輯的特點， epf10k10a的邏輯採用邏輯圖輸入的方式，並在max plus11卜模擬結果。
  10. To realize nolinear excitation controller, it must be improved that the disposal speed of nolinear excitation control " s signal. with analyzing and comparing all kinds of microcomputer excitation controller, a new microcomputer excitation control scheme is offered that is based on dsp controller while the cpld chip is utilized for realizing the function of pulse trigger. it is described in detail that the method of realizing controllable silicon digital logic by verilog hardware describe language and the designed digital pulse trigger " s veracity was validated by digital simulation

    論文進一步針對非線性勵磁控制要求信號處理速度高、信息量大的特點，在對目前微機勵磁控制器分析基礎上，提出採用dsp控制器晶元作為核心處理器的微機勵磁控制器的解決方案，運用復雜可編程邏輯器件cpld晶元實現可控硅同步脈沖觸發單元，並簡要說明了verilog硬體描述語言和數字脈沖形成邏輯的方法，通過電路數字模擬對所設計的數字觸發單元進行了驗證。
  11. In the paper we amply introduce the logical structure and design of software and hardware of the virtual multi - channel instrument system for temperature measurement. applying the object oriented programming ( oop ) method, center control module, transmitter demarcating module, channels and scopes module, data collection and process module, data analyze module, data display module, data redisplay module, print module and the other auxiliary functions are designed, which realize the collection, process, analyze and display of the powerful virtual instrument

    在本文中，作者詳細介紹了虛擬式多通道溫度測試儀系統的邏輯結構和軟硬體設計，運用面向對象（ oop ）的軟體設計方法，通過中心控制模塊、變送器標定模塊、測溫通道和測溫范圍設置模塊、數據採集與處理模塊、數據分析模塊、數據顯示模塊、數據回放模塊、列印輸出模塊和其他輔助功能模塊的設計，實現了對溫度信號進行採集、處理、分析和顯示的功能很強的虛擬測溫儀器。
  12. Then we explicate the hardware design in details, including implementing ad convert, extending multiple serial communications and external memory, and using cpld do some logic controls. thereby we implement abundance simulation interface, flexible digital interface and serial communication interface. at last we describe the software design, including software design of cpld basing on vhdl and software design of dsp

    本文首先介紹飛行模擬訓練系統的主要組成；接著說明飛控計算機整體系統方案的設計；然後詳細說明飛控計算機硬體平臺的設計，包括ad轉換、多串口通信、外部存儲器的擴展以及採用可編程邏輯器件cpld實現電路的邏輯控制等幾部分，體現了系統豐富的模擬介面、方便靈活的數字介面和串列通信介面；最後是軟體部分的編程，包括cpld部分的硬體描述語言程序設計，和dsp部分相關的程序設計。
  13. The programmable logic device is programmed and simulated vvith max + plus ii of altera corporation, and the program is down loaded to the device through byteblaster parallel port dovvnload cable

    可編程邏輯器件由altera公司的max + plus編程並模擬，由所製作的並口傳輸電纜線下載到硬體。
  14. In the hardware, the conversion from serial port, parallel port or usb port to jtag port is realized by a cpld component, by which the volume of the emulator can be reduced and its reliability can be enhanced as well. the feature of this paper is the design of software section

    硬體部分主要採用了cpld器件來實現串口，並口， usb口到jtag口的邏輯轉換，採用cpld器件來實現此轉換功能不但減小了模擬器的體積，而且還增強了模擬器的可靠性。
  15. A testbench program is edited to simulate the behavior of the fifo. after the software simulation is accomplished, a real hardware circuit is designed to multiplex two data channels ( 1553b data channel and 1394 data channel ) according to ccsds standard. during the experiment and hardware debugging, the output logic of the fpga is checked up

    設計中，用vhdl語言對高速復接器進行行為級建模，為了驗證這個模型，首先使用軟體進行模擬，通過編寫testbench程序模擬fifo的動作特點，對程序輸入信號進行模擬，在軟體邏輯模擬取得預期結果后，繼續設計硬體電路，設計出的實際電路實現了將來自兩個不同速率的信源數據（ 1394總線數據和1553b總線數據）復接成一路符合ccsds協議的位流業務數據。
  16. 1. a small and cheap 8 - bit microcontroller is used as control core. all components of the sensor, some of which are necessary for the multiple and intelligent functions, are selected ones with low cost and small package. by designing all auxiliary logic circuits in a complex programmable logic device ( cpld ), and integrating all analog circuits in an application specific ic ( asic ), the size of pcb board is greatly reduced, which make it possible that the pcb can be installed with the displacement detector together

    系統採用小型廉價8位微控制器控制，電路內配置了為實現多功能智能化所必需的硬體，並全部採用低價格、小體積器件，還將所有輔助邏輯電路設計在一片復雜可編程邏輯器件cpld內，所有模擬電路集成於一片專用集成電路asic內，大大縮小了電路板尺寸，再與傳感元件組裝在一起，從而使整個系統在保證智能化功能的前提下，具有體積小、成本低、一體化和抗干擾能力強的特點。
  17. In the hardware design, the analog circuit, high - speed a / d convertor, storage control logic and vxibus interface are discussed. the results of the simulation and analysis of the circuits are given

    在模塊的硬體電路設計部分中，著重對信號調理電路、高速a / d轉換器、高速存儲邏輯控制以及vxi總線介面等內容進行了討論，給出了具體的電路設計和關鍵器件的說明，並對部分模擬電路和數字電路進行了模擬分析。
  18. And more than 70 % hardware are tested during microcode self - test since the execution of micro program can cover other data paths. boundary scan is designed according to ieee1149. 1, and some other instructions such as degug, runbist are provided to support internal fault testing, online debugging and built - in self - test besides the several necessary insructions. internal scan is implemented by partial scan, through this the boundary of logic component and user - cared system registers can be selected to be scanned

    Bist用於測試cpu的微碼rom ，其它ram則利用微碼rom中的微程序進行測試，而微程序的運行則可以順帶覆蓋其它數據通路，從而使高達70 %的硬體得到測試;邊界掃描按ieee1149 . 1標準設計，除必備的幾條邊界掃描指令外，還提供了debug 、 runbist等指令以支持內部故障測試、在線調試及內建自測試;內部掃描採用部分掃描策略，選擇邏輯部件的邊界及用戶關心的系統寄存器進行掃描，從而實現了硬體邏輯劃分，方便了后續的測試碼產生和故障模擬，並為在線調試打下了基礎。
  19. In the process of design, simulation is achieved by active hdl, and synthesis is achived by symplify, and finally the chip is downloaded in quickpro

    在硬體邏輯設計過程中，藉助activehdl進行硬體邏輯前後模擬，使用symplify工具進行邏輯綜合，最終在quickworks下生成fpga晶元。
  20. Based on the above study, this topic has realized simulator run environment. after the start - up of simulation running environment with loaded object code, each simulation component shall harmonious run under the logic control of application software, so as to support the software commission and test verification

    支持從構件庫中選取需要的模擬構件，以可視化圖形編輯的方式構造模擬目標硬體環境;加載目標碼的模擬運行環境啟動后，各模擬構件能在應用軟體邏輯的控制下協調運行，從而支持嵌入式系統軟體的調試和測試驗證。
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