編碼器譯碼器 的英文怎麼說

中文拼音 [biānmǎqìyìmǎqì]
編碼器譯碼器 英文
codec
  • 編 : Ⅰ動詞1 （編織） weave; plait; braid 2 （組織; 排列） make a list; arrange in a list; organize; gr...
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 譯 : 動詞（翻譯） translate; interpret
  • 編碼器 : （將一項信息變換成一系列數碼信號的電路） coder; encoder; encipheror編碼器方框圖 encoder block diagram
  • 編碼 : encoded; code; coded; encrypt; codogram; coding編碼表 encode table; 編碼程序 builder; 編碼尺 code...
  1. Research on coding method for matrix axile angle encoder based cpld

    矩陣式編碼器譯碼方法的研究
  2. The contents adds the to code the system ". the colloquy dvd sees the arithmetic figure to add the project. only the that the dvd that css admit to broadcast the to can just break password see data

    「內容加密編碼系統」 。正式的dvd視頻數字加密方案。僅css許可的dvd播放器才可以破譯視頻數據的密碼。
  3. Chapter 3 discusses the modules used in the fh - mpsk and fh - / 4dqpsk systems. these modules include : duc / ddc ( digital up converter / digital down converter ), nyquist flitter, burst start detection, interpolation module, pll ( phase locked loop ), pll error extraction, initial phase correction and the coding and decoding for tcm

    第三章主要討論了跳頻模式下fh - mpsk和fh - 4dqpsk系統中各個模塊的設計，這些模塊包括：上下變頻器、奈奎斯特濾波器、信號到達檢測、插值模塊、通用環路、各環路誤差提取方法、初始相位校正和tcm編譯碼。
  4. Jx5 is a complex microprocessor, which contains cache, microcode rom, instruction prefetch unit, instruction decode unit, integer unit, mmx unit, floating point unit, page unit, bus unit, dp logic, apic and so on. it is very difficulty to test a such complicated microprocessor and receive anticipative fault coverage ratio. so, we must add dft in cpu ’ design

    Jx5微處理器是一款結構異常復雜的微處理器，它的內部包含有: cache 、微碼rom 、指令預取部件和動態分支預測部件、指令譯碼部件、整數部件、多媒體部件、浮點部件、分段和分頁部件、總線介面部件、雙處理器介面部件、可編程中斷控制部件等。
  5. Turbo codes represent the new code structures, which consist of pccc ( parallel serially convolutional code ) and sccc ( serially concatenated convolutional code ). in this paper, the background of turbo codes are firstly introduced, which includes the base principle of error correction code 、 block code and convolutional code ; the principle of turbo code and the iterative decoding is secondly expanded ; the key decoding algorithm : a revised map algorithm and iterative decoding theory are detailed ; then, a new turbo code structure : hccc ( hybrid concatenated convolutional code ) is presented, and the capacity of this code method is analyzed, the average capacity upper bound is derived ; at last, this code is simulated on awgn ( additive white gaussian noise ) channel and rayleigh fading channel

    本文首先介紹了turbo碼的背景知識，包括差錯控制的基本原理、分組碼和卷積碼；然後闡述了turbo碼的基本原理，包括turbo編譯碼器結構及迭代譯碼原理；較為詳細地描述了關鍵的譯碼演算法： ?種改進的最大后驗概率（ map ）譯碼演算法及迭代譯碼演算法；提出了一種新的turbo碼結構：混合turbo碼（混合級聯卷積碼） ；並用編碼性能聯合界分析方法對混合turbo碼進行了性能分析，得出了其平均性能上界；並在高斯白噪聲通道和瑞利衰落通道上分別作了一些應用研究及計算機模擬實驗。
  6. Generates code for the specified code document object model codedom compilation unit and sends it to the specified text writer, using the specified options

    為指定的代碼文檔對象模型（ codedom ）編譯單元生成代碼，並使用指定的選項將代碼發送到指定的文本編寫器。
  7. Generates code for the specified code document object model codedom compilation unit and outputs it to the specified text writer using the specified options

    為指定的代碼文檔對象模型（ codedom ）編譯單元生成代碼，並使用指定的選項將代碼輸出到指定的文本編寫器。
  8. The encoder and decoder used in atm switcher are designed using specific error correcting 1c

    設計了atm交換機中編譯碼器模塊。
  9. 5. according to the euclidean algorithm rs encoder and decoder are implemented in fpga

    根據euclid迭代譯碼演算法，用fpga設計實現了rs碼編譯碼器。
  10. The decoder is compiled and simulated in ep1c12q240c by quartusii - 5. 0. the different error style is added to the sequence received in emulated channel. correspondingly, the correct decoding results are attained at the output terminal

    在quartusii - 5 . 0模擬環境下以cyclone系列的ep1c12q240c為目標晶元對譯碼器進行了編譯和模擬，在接收序列中加入不同的錯誤類型，相應的在譯碼器輸出端得出了譯碼后的正確譯碼結果，驗證了設計方案的正確性。
  11. Evaluation package for mpeg - 2 coder and decoder show its appearance on the market

    2編譯碼器評價組件亮相
  12. Enhanced variable rate codec speech service option 3 for wideband spread spectrum digital systems

    寬帶頻譜擴展數字系統用增強的可變率編譯碼器語音服務選擇3
  13. Finally, a total design scheme that realizes the stbc is shown and the software which supports the platform is also given

    之後，給出了空時分組碼編譯碼器的硬體總體設計方案，闡述了軟體的具體實現過程。
  14. Therefore, the research targets of this dissertation are to realize the coding and the decoding of stbc after studying its theory

    本文在研究了空時分組碼的理論基礎上，對其編譯碼器進行了硬體模擬實現。
  15. Evrc 3 software distribution for tia - 127 - a - enhanced variable rate codec speech service option 3 for wideband spread spectrum digital systems

    Tia - 127 - a的軟體配置.寬帶頻譜擴展數字系統用增強的可變率編譯碼器
  16. Although the structure of stbc decoding is very simple, it can achieve the same diversity gain as the method of mrc, and its use of the spectrum is very high. because of these advantages, sttb is referred into the 3gpp1

    由於空時分組碼編譯碼器的結構相當簡單，卻能獲得與最大比合併相同的分集增益，並且它的頻譜利用率高，已經被引用到3gpp1中。
  17. Chapter 5 gives the design illumination of the rs coder and decoder based on fpga. then it gives the integrated results for realization design of the rs ( 31, 15 ) error - correcting code. after that, it gives the functional and layout simulation results for the limited field multiplier, divider, rs coder and rs de - coder

    第五章給出了基於fpga實現的rs編碼器和譯碼器設計說明， rs （ 31 ， 15 ）糾錯碼設計實現的綜合結果，有限域乘法器、除法器、 rs編碼器、 rs譯碼器的功能模擬和布局布線后模擬結果，最後總結主要的調試經驗。
  18. After a great amount of detailed computer simulations and concise qualitative and quantitative theoretical analysis, the turbo codes " parameters and fpga specific hardware implementation architecture suitable for being integrated into dtv systems are determined. furthermore, the codec is completely designed with verilog hdl, ending with an occupation of less than a 600 - thousand - gate fpga chip. at this lowest hardware cost, a white noise snr threshold of 1. 8db at a net stream rate of 6mbps is achieved, which exceeds all other existent dtv systems " performance

    經過大量詳細的計算機軟體模擬和簡明扼要的定性與定量的理論分析，最終確定了數字電視系統中適合採用的turbo碼參數及針對fpga特殊構架的硬體實現結構，並用verilog硬體描述語言完成了turbo碼編譯碼器的完整設計，以佔用不到一片60萬門fpga晶元的較少的硬體資源取得了在6mbps凈碼率下1 . 8db的白噪聲信噪比門限這一遠遠超過現有任何數字電視系統的性能。
  19. However, in the part of the software, the schemes to programme coder and decoder are expatiated separately and the final flow charts are drawn after that. during the design of the coder, the selection of the information source and the modulation is discussed. according to the characteristic of the multi - phase modulation ml

    在軟體實現部分，分別詳述了編碼器和譯碼器的編程方案並給出了最終實現的流程圖:編碼器的設計中論述了信息源和調制方式的選擇方法;而對譯碼器的最大似然演算法則根據多相調制的特點進行了演算法簡化和實現。
  20. In the third chapter, the principles of randomizer and de - randomizer are illuminated, and the hardware realization is also given. the fourth chapter is focused on the design of ip ( intellectual property ) and the analysis of the principle of rs encoding and decoding. based on the theory of design reuse in soc ( system on chip ), this chapter is devoted to the design and implementation of rs decoder ip which can be implied in three hdtv channel decoder standard

    第四章首先介紹了ip的基本知識和設計流程，接著對rs碼的編碼和譯碼進行詳細的理論分析研究，提出rs編譯碼器實現方法，然後根據soc可復用設計設計思想，設計了一個應用於hdtv通道解碼的rs譯碼ip核，最後給出dvb - crs譯碼器的asic設計，並給出了其規模和性能。
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