解碼單元 的英文怎麼說

中文拼音 [jiěmǎdānyuán]
解碼單元 英文
du decode unit
  • 解 : 解動詞（解送） send under guard
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 解碼 : decoding; decipher; decode
  1. On the basis of the study on the speech coder algorithms, paper describe an advanced method of developing dsp system software, and as the guidlines, we developed the programme of whole decoder unit. paper stress on analysis of the ecu in decoder unit. aiming at amr algorithms disadvantage of angularity of synthetical speech, paper study on the specutral extrapolation which apply to extrapolate reflect coefficient of track model to make error conceal processing of amr. at last paper analyze existing echo cancellation algorithms using on mobile communication system

    在此基礎上，描述了一種較為先進的大型dsp系統程序開發策略，並以此為指導思想，以美國ti公司c6000dsp開發平臺開發出了整個amr解碼器單元的系統程序。論文對amr解碼器的誤碼隱藏處理單元進行了重點分析，針對原有演算法合成語音自然度不好的缺點，論文研究了將譜外推法應用到amr演算法中外推出聲道模型反射系數參數進行誤碼消除處理。
  2. The control system included the following units : video decode unit, data format conversion unit, fpga controller, cache unit and d / a monitor. the above self - design control unit plus row and column power supply units make the whole fed driving system, thus drove the 25 inch sample and realized color video display. the 25 inch vga sample thus fabricated could display video images, and obtained its brightness 400cd / m2, contrast ratio 1000 : 1, 256 circuit gray scale

    本文介紹了fed驅動系統的工作原理，重點論述了基於fpga的vga級彩色fed新型驅動控制系統的研製，這種新型fed驅動控制系統主要包括視頻解碼電路、數據格式轉換電路、 fpga控制電路、數據緩存電路和d / a監控電路，配合后級列灰度調制單元和行掃描單元，組成完整的fed驅動系統，可以驅動25英寸vga級fed顯示屏，實現彩色視頻顯示，樣機亮度達400cd / m2 、對比度為1000 : 1 ，灰度等級為256級。
  3. The catv charge and control system is mainly composed of the management software 、 the header data modulator and the terminal charge and control equipment. i am responsible for design catv charge and control equipment and test system. the header data modulator is used to encrypt the control single from computer and transmit it into the appointed frequency. the terminal charge and control equipment demodulate out the control single from data modulator and transmit it to the addressing control part, where the demodulated fsk single is received and well - handled by the cpu unit, decode the unauthorized signals and deliver it to the shut point, shut point make use of capability of wideband anf characteristic of shut, then the signal of illegal customer will be turn off and vice versa, the legal customer can receive the normal signal

    前端數據調制器完成對計算機輸出的控制信號加密處理，將指令碼載送到一指定頻率點。終端收費控制器解調出控制信號，送至單片機尋址控制部分。單片機尋址控制部分接收經fsk數據解調器送來的信號，送入cpu單元后，解出不授權信號，然後向關斷部分送入信號，關斷部分利用pin二極體的寬帶工作能力以及關斷特性，實現對非授權用戶或者非法用戶的信號關斷，使之不能正常收視，繳費用戶進行開通正常收視，達到控制用戶通道的管理。
  4. This paper introduces a project based on code division multiplexed that is used to realize four el channels ' s wireless transportation. after briefly introducing the whole structure of the device of transportation, this paper introduces mainly implemention of the hardware. futhermore, the discussion concerning the selection of principles in code acquisition and the threshold setting of code acquisition on continous pilot in the receiving unit is given. at the same time, the methods about how to design the parameters of dll is introduced in this paper. in addtion, how to solve the actual problems in debugging the hardware is also provided

    本文提出了一種基於碼分復用技術的四路e1數據擴頻無線傳輸設備的實現方案。在介紹整個擴頻數傳設備實現框圖的基礎上，重點介紹了硬體平臺的實現；接收單元捕獲策略的研究及其捕獲門限的確定方法；以及接收單元dll環路參數設計方法；並給出了調試過程中遇到的實際問題及其解決措施。基於調試所遇到的問題，論文的最後提出了這套數傳設備的改進方案。
  5. Aiming at the g code widely used in industrial control, the special explain procedure is programmed to make the control unit more common

    針對當前工業控制中廣泛應用的g代碼，編制了專門的解釋程序，使得控制單元的通用性進一步加強。
  6. The functional model and information model are built with idef base on the basic model for bom management. this dissertation thoroughly analyzes the key modules of bom management. the solution for computer coding is brought forth, and the dynamic model of process management is put forward, and the solution for static privilege management and dynamic privilege management is brought forward

    然後以bom管理原理模型為基礎，利用idef的方法建立了bom管理的功能模型和信息模型，並對bom管理相關關鍵單元模塊進行了詳細分析，提出了計算機編碼的解決方案，給出了bom配置設計時使用的動態流程管理模型，並給出了bom管理的動態權限管理和靜態權限管理的實現方案。
  7. When the system is implemented by fpga, the software can be downloaded from our host pc, and the data can be saved in fpga

    在fpga實現的環境中，系統軟體可以從pc機下載，存儲mp3數據流文件，由整數運算單元完成解碼工作后通過codec播放。
  8. The system is consist of the main data processing board which is based onthe fpga device and fast ethernet phyceiver rtl8201l and a - law pcm data encoder and decorder chip msm7702 - 3, and the dial - up and display board which is based on mcu. the main board would carry out the core task of data processing, such as voice data packing and unpacking, the ethernet frame processing, protocol processing, call processing, etc. the dial - up and display board would carry out the task of display the ip address which is input by consumer and status of network during talk period from the main board, and so on. in the paper the system of lan ip telephone and the tcp / ip protocol is introduced firstly, then the fpga device is stated. after that the fpga - based hardware scheme is introduced in detail in chapter four

    系統以altera公司的acex1k系列的fpga和快速以太網控制器rtl8201l和語音編解碼晶元msm7702 - 3為核心構建了數據處理主板和以單片機為控制器的撥號顯示子板組成。數據處理主板的核心任務，包括語音數據處理、以太網幀處理、協議處理、呼叫處理等。撥號顯示子板則完成通話前的顯示用戶所撥過的ip地址，通話期間網路狀態的顯示等等。
  9. Based on output wave of hs2260 encoding chip, this paper analyzes the encoding features of this chip and come up with the specific method of auto - adapted baud rate decoding of this chip by mcu and the method that was used in the long - click and double - click events recognition that was applied in remote controllor by this chip

    從hs2260編碼晶元的輸出波形入手，分析了該晶元的編碼特徵，提出了使用單片機對其進行自適應波特率解碼的方法，同時也提出了該晶元在遙控器應用中的長鍵及雙擊動作的識別方法。
  10. Finally we have considered an example in java and based on its ecfg, applied these cases to arrive at the e - cc of the total system as well as proposed a methodology for calculating the basis set, i. e., the set of independent paths for the oo system that will help in creation of test cases for code testing

    這會對代碼測試產生測試用例帶來幫助。在cfg被用做單元測試的同時， ecfg也會用作對所有面向對象軟體類的綜合測試。最後，我們在一個用java編寫的代碼例子上應用我們的模型，計算ecc和基礎集合去證實我們的解決方法。
  11. As conforming with the h. 323v2 and relevant national standards, the terminal has high interoperability with other h. 323 device, and has some main function units defined by standards such as system control unit, h. 225 layer unit, lan interface unit, and audio codec unit

    323國際標準第二版和相關國內標準，能夠和其它h 323設備互通，具有系統控制單元、 h 225layer單元、網路介面單元和語音編解碼單元等協議中所規定功能單元。
  12. Id instruction decoder. this unit is capable of decoding up to 3 instructions per cycle

    命令解碼。本單元每循環能解三條指令。
  13. There is two questions on transferring the video signals from the output of the hdtv decode to display on the screen, one is that we should convert the video data into many different video formats which is named as format conversion function

    經hdtv視頻解碼器解碼后的視頻信號在送去電視機顯示前需要解決兩個問題；一是對輸入的視頻格式可能做的視頻格式轉換（及yuv到rgb色度空間變換，稱為格式變換單元。
  14. Moreover, video control program to implement internal function of fpga is designed including video capture time sequence control, ping - pang frame buffer read and write time sequence control and lcd display time sequence control, and program ' s simulation and analysis is also provided. at last, this paper presents a portable iv ' s video processing system, and proposes three buffer strategy to control capture buffer. and a moving object detection algorithm of combing an adaptive background subtraction technique with a three - frame differencing is adopted

    設計了基於fpga系統結構的車載視頻顯示電路板；利用單片機io口模擬i2c時序，實現了視頻解碼晶元控制；利用fpga實現視頻控制，研究了採集通道時序控制、雙幀存ram讀寫時序控制及lcd顯示時序控制的方法，並進行了軟體模擬和分析；設計了車載視頻檢測系統方案，給出了管理採集緩沖區的三幀緩沖策略，採用綜合三幀差分和自適應背景相減的演算法實現運動檢測，連通體檢測去除虛目標，模擬實驗證明其有效性，同時分析了該演算法在dsp視頻檢測系統中的簡單實現方法。
  15. These sensors make up of a network for signal detection, muti - step transmission is used to transmit the signal, and self - examination is a useful function for each unit. 2

    三種傳感器在一定范圍內組成一個探測網路，網路中的各探測單元利用自行設計的多級傳輸的方法傳遞信息，解決了傳輸中的編碼及時序問題，設計了具體電路。
  16. On the basis of analyzing the old system and theory, the element circuits of wireless digital audio transceiver modules are designed in detail including the digital audio encoding and decoding circuits with the surrounding circuits, the fsk circuit based on pll frequency synthesizer, the power amplifier circuit, the frequency discrimination and agc circuit

    在分析原系統結構和理論的基礎上，完成了整個無線數字音頻傳輸模塊各單元電路的設計。主要包括有數字音頻編碼和解碼電路及外圍電路的設計、基於鎖相頻率合成器理論的fsk電路設計、功率放大器的設計、鑒頻與agc控制電路的設計。
  17. This dissertation is concentrated on the design of ess decode project, which make use of mpeg decode ic ess6425 as the core supported by other ic cs4340 ( audio ic ), gl811 ( usb 2. 0 to ata / atapi bridge controller ), etc. on the basis of the decode project, a multi - media mp4 hd player is designed with special features of convenient installment, competitive price and perfect performance

    本研究以美國ess公司的mpeg專用解碼晶元es6425為核心整合其他輔助晶元如cs4340 （音頻處理晶元） ， gl81 （ 1usb2 . 0toata / atapibridgecontroller ）等，設計出一款mpeg - 4多媒體播放器，該播放器具有安裝簡單、價格低廉，功能全面等特點。
  18. The paper makes great efforts on the software optimization of evrc vocoder. based on the understanding of tms320c64xx cpu structure, we do deeply - optimization on the loop which appear usually in voice signal processing, and this improve the utility ratio of cpu and the parallelity degree of cpu function cell. at the same time, we utilize the bit - exact test to test the fixed - point evrc vocoder with the test vectors of tia / eia / is - 718, which improve the robustness of the vocoder

    本文圍繞定點evrc聲碼器的軟體優化，做了大量的工作，在充分理解tms320c64xxcpu結構的基礎上，針對語音信號處理中大量出現的循環運算進行了深度優化，大大提高了cpu的利用率以及cpu功能單元的并行程度，同時，我們還用tia / eia / is - 718的測試向量對定點evrc聲碼器進行了嚴格比特對準測試，提高了聲碼器的魯棒性。
  19. The main assignments are : accomplished the design of transmitter, receiver, coder and decoder module, control system of obu and rsu. the communication protocol and the main factors which would influence the communication are also discussed

    主要工作內容為:完成了車載通信單元和路側通信單元光發射機、接收機、編碼解碼模塊以及控制系統的設計，並討論了通信協議的相關內容和影響通信的主要因素。
  20. In this paper, we briefly introduced the performance of wave coding and vocoder, emphasizedly studied the principle and performance of variable rate vocoder q4401, including the internal construction and pins, qcelp coder & vocoder, pcm interface, cpu interface initialization process, command format and so on. we also designed a application circuit, with the experiment validated its performance. in this design, the pcm interface chip is tp3057, it was used to finish a / d transform, the compress coding was finished by q4401, the initialization and control were accomplished by 8051 singlechip

    重點是研究變速率語音編解碼晶元q4401的工作原理及性能。其中包括q4401的內部結構及管腳、 qcelp編碼方式、 pcm介面、 cpu介面、初始化過程、命令格式等，並在此基礎上，設計一個實際的應用電路，通過實驗，驗證其性能。在設計中用pcm介面晶元tp3057來完成從模擬信號到數字信號的轉換，再由q4401進行壓縮編碼，對q4401的初始化及控制由8051單片機來完成。
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