解碼電路 的英文怎麼說

中文拼音 [jiěmǎdiànlù]
解碼電路 英文
decoding circuit
  • 解 : 解動詞（解送） send under guard
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 解碼 : decoding; decipher; decode
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. The control system included the following units : video decode unit, data format conversion unit, fpga controller, cache unit and d / a monitor. the above self - design control unit plus row and column power supply units make the whole fed driving system, thus drove the 25 inch sample and realized color video display. the 25 inch vga sample thus fabricated could display video images, and obtained its brightness 400cd / m2, contrast ratio 1000 : 1, 256 circuit gray scale

    本文介紹了fed驅動系統的工作原理，重點論述了基於fpga的vga級彩色fed新型驅動控制系統的研製，這種新型fed驅動控制系統主要包括視頻解碼電路、數據格式轉換電路、 fpga控制電路、數據緩存電路和d / a監控電路，配合后級列灰度調制單元和行掃描單元，組成完整的fed驅動系統，可以驅動25英寸vga級fed顯示屏，實現彩色視頻顯示，樣機亮度達400cd / m2 、對比度為1000 : 1 ，灰度等級為256級。
  2. The parallel form of the input sequence is decoded by means of a logical decoding circuit.

    此并行形式序列通過邏輯解碼電路輸入。
  3. The channel counter and decoder provide the channel select information to the data latch and transmit logic circuits.

    通道計數器和解碼器向數據鎖存和傳送邏輯電路提供通道選擇信息。
  4. The paper is to design analogue lowpass filtering circuits with high performances. the circuits are used directly as anti - alias filters in an analogue front - end of video decoder ic ( integrated circuit )

    =本文旨在設計高性能的模擬低通濾波電路，用作視頻解碼晶元模擬前端中的抗混疊濾波器。
  5. Dvb / mpeg - 2 transport stream multiplexer / demultiplex takes an important role in digital video broadcasting system. it can combine several transport streams from source encoder into a single transport stream to transport channel, or demultiplex trasnsport stream into one program sorce to source decoder. its performance has a great influence on the program transmission ability of hdtv system and the decoding quality of decoder in hdtv receiver. mpeg - 2 system multiplexer signalized video, audio, host data and so on to fixed length packet type for making transport stream

    Dvb mpeg - 2傳送流復用解復用是數字電視廣播系統中的重要組成部分之一，它將從信源編碼器輸出的多路節目源復用成一路傳輸流送入傳輸通道，或者從通道中包含多路節目源的一路傳輸流中解復用出一路節目送到解碼器解碼。
  6. The encoder and decoders in the paper has been tested on the circuit board using the altera ’ s fpga of stratix gx ep1sgx25df672c7 with the system clock of 125mhz

    本文的編解碼器採用altera公司的fpga晶元stratixgxep1sgx25df672c7在系統時鐘125mhz的情況下完成了電路板測試。
  7. In the modulation / demodulation circuits, cpld is selected as platform of the digital logic part, which includes series - shunt / shunt - series transform, difference coding and sample verdict

    調制/解調電路中，串並/並串變換、差分編/解碼和抽樣判決等數字邏輯部分是以cpld作為開發平臺，論文給出了實現上述功能的vhdl程序及模擬、測試結果。
  8. Detail specification for electronic component. semiconductor integrated circuit - type cd 7343 gs phaselocked loop fm stereo decoder

    電子元器件詳細規范.半導體集成電路cd 7343 gs型鎖相環調頻立體聲解碼器
  9. There are several aspects of work that was done in this thesis mainly. firstly, the theory of the under - water long - range remote control system was analyzed and the remote control instruction code was designed. secondly, decoding circuit of the under - water long - range remote control system was designed with fpga, including vhdl coding, simulation, synthesis, place & route, etc. besides, power consumption to fpga that is designed is estimated in this thesis. lastly, we designed and made one pcb to verify and test fpga decoding chip that is designed, and debugged and tested it finally

    首先，深入研究和分析了在頻域實現水下遠程遙控解碼的原理並進行了遙控指令編碼設計；其次，用altera公司的cyclone系列fpga晶元完成了水下遠程遙控fpga解碼晶元的設計工作，包括硬體描述語言（ vhdl ）編碼、電路前後模擬、綜合和布局布線工作，並對設計的fpga解碼晶元進行了初步的功耗估算；最後設計製作了一塊fpga解碼晶元電路驗證測試板，並完成了電路調試和測試。
  10. The system is based on a ' subaudible ' tone injected after the audio stages into the transmitter during encode and the tone is detected before the audio circuits in the receiver

    這套技術的基本原理如下，進行編碼（調制）的時候，一個「亞音」音頻信號被注入聲音信號，並在接收端的音頻電路前檢測這個音頻信號解碼。
  11. Based on the realization of the encoder / decoders, this scheme aims at the highest rate downstream frame, and has realized the parallel fec circuit and scrambler complying with the protocols and maken a simulation. the fprme decoder is advanced in the world. the parallel fec circuit completely conforms to the itu - t protocols, and has important practical value

    在rs （ 255 ， 239 ）硬體編碼器/解碼器實現的基礎上，本文按照gpon協議要求，針對gpon中最高速率2 . 488gbps的下行幀，通過設計復雜的操作時序，實現了符合協議規定的32位并行fec編解碼和解擾碼電路，並作了模擬。
  12. Colour decoding circuit

    彩色解碼電路
  13. 2. quick check and verify for address decoding or data transceiver circuits, which designed

    2 .可快速驗證cv - 16解碼電路之8bit或16bit資料讀寫值是否正確
  14. After being hdl simulated and fpga verified, the itu656 decoder worked in decoding function

    經hdl模擬及fpga驗證， itu656解碼電路實現了數據解碼的功能。
  15. By systemview, hdl simulation and fpga verification, the results showed that the decoder met commercial ic requirements

    經systemview ， hdl模擬及fpga驗證，結果表明:所設計的數字視頻解碼電路的各項性能達到了晶元商用要求。
  16. According to theories of television and the video format of itu601 and itu656, the itu656 decoder and digital video decoder were designed

    依據電視技術的基本原理及itu601 、 itu656標準的視頻格式，完成了itu656解碼電路和數字視頻解碼電路的設計。
  17. The chapter of hardware design first expounds the whole design. the several primary circuit are designed, including power circuit, controlling circuit, detecting circuit and the dsp quadrature encode circuit

    硬體部分先作了整體設計的論述，然後具體介紹了功率電路、控制電路、檢測電路以及dsp的正交解碼電路。
  18. The results of p & r demonstrate that this design constructs a rs encoding / decoding circuit with a 3. 2k internal fifo cache embedded, at the scale of 46k gates. its encoding and decoding speed are 66mhz and 47mhz respectively

    布局布線后結果表明本文所設計的rs編碼器的速度可達到66mhz ；解碼速度可達到47mhz ，電路規模為4 . 6萬門，包含有3 . 2k的內部緩存fifo的rs編/解碼電路。
  19. The results of the hdl simulation and fpga verification showed that image enhancement improved greatly the image quality. cooperating with software a circuit that can read and write flash memory and a remote controller hardware decoder were also designed in this thesis. after hdl

    本文還設計了與軟體配合能讀、寫閃存的電路以及紅外遙控的硬體解碼電路，經hdl模擬及fpga驗證，所設計的兩種電路能完全滿足晶元商用要求。
  20. On the basis of analyzing the old system and theory, the element circuits of wireless digital audio transceiver modules are designed in detail including the digital audio encoding and decoding circuits with the surrounding circuits, the fsk circuit based on pll frequency synthesizer, the power amplifier circuit, the frequency discrimination and agc circuit

    在分析原系統結構和理論的基礎上，完成了整個無線數字音頻傳輸模塊各單元電路的設計。主要包括有數字音頻編碼和解碼電路及外圍電路的設計、基於鎖相頻率合成器理論的fsk電路設計、功率放大器的設計、鑒頻與agc控制電路的設計。
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