譯碼電路 的英文怎麼說

中文拼音 [yìmǎdiànlù]
譯碼電路 英文
decoder circuit
  • 譯 : 動詞（翻譯） translate; interpret
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. Bcd detail specification for electronic component. semiconductor integrated circuit. type ch2019 4 - line to 10 - line decoder with bcd - in

    電子元器件詳細規范.半導體集成電路ch2019型4線- 10線譯碼器
  2. The dac consists of analog circuit blocks and digital circuit blocks, so it is a mixed signal circuit. because the digital part is simple comparatively, we use the same method as analog part to design it

    採用模塊化的設計方式實現數據快速轉換，主要包括電流源矩陣模塊、鎖存模塊、譯碼模塊、帶隙基準電壓源模塊及電流開關網路等電路模塊。
  3. Each unit is extracted from the circuit, and is analyzed detailedly in framework, configuration and design approach. the instruction system of c9821 is unscrambled and then the instruction decode algorithm are obtained. the complete program of c9821 including basic arithmetic and root square operation is realized

    在軟體方面，破譯了c9821的指令系統，分析了指令譯碼電路的設計技術，分析了計算器內bcd碼的四則運算及開方運算演算法，得到了實現c9821全部功能的程序，掌握了該計算器的程序設計方法。
  4. In the part, there are following contents : single - chip and memory circuit, interrupt control circuit, decoding circuit, parameter area circuit, watchdog circuit and serial communication interface circuit, etc. in this paper, serial communication interfaces between upper pc and lower single - chips are designed

    其中，微處理器的設計是關鍵。在微處理器部分的設計中，主要包括以下內容：單片機及存儲器電路設計、譯碼器電路設計、參數區電路設計、中斷控制電路設計、看門狗電路設計、串列通信介面電路設計等。
  5. The circuit of assembling frame and splitting frame based on ram and fifo are designed ( realized frame synchronization ). the two 3b4b converting circuits are designed ( realized one circuit ). the nrz, rz, manchester code converting circuits are designed

    4 、設計了基於fifo和ram的兩種組幀和拆幀電路（實現了幀同步碼檢出） ；設計了兩種3b4b編譯碼電路（實現了一種） ，針對nrzi 、 rz和曼碼各設計了一個編譯碼電路。
  6. So the complexity of lfrr is low. a hardware implementation for lfrr is proposed. parallel comparator and encoder lead to a fast construction of schedule table

    本文還提出了一種用硬體電路構造調度表的方法，採用并行比較加譯碼，可以很快構造出循環調度表。
  7. In this paper we discuss mca circuit, the sequential logic for mca data collection, for the setting of the uld, lld and the gain of pga, as well as the combinational logic for decoding circuits of the computer interface, based on cpld

    本文詳細論述了利用cpld實現的脈沖幅度多道電路及其數據採集的時序控制邏輯、閾值設定和程式控制放大倍數設定的時序控制邏四川大學碩士學位論文輯、以及與計算機介面的譯碼電路等組合控制邏輯。
  8. Concretely, on the basis of describing the communication specification of arinc 429 with enhanced parallel port ( epp ), the standard and the module application of dsp and cpld, the thesis has proposed the design of the arinc 429 technology based on dsp system. at first, the function and the application of each module of the system and the operation principle of high - performance cmos bus interface circuit hs - 3282 chip which forms the main body of the data diversion of the interface module are introduced. secondly, the hardware structure of the interface module is described in detail, mainly including data latch and buffer circuit, choice circuit of transmission rate, etc. and then the design philosophy and flow charts of the software are fully discussed, such as the basic requirement of software, the design and realization of the function

    本文在簡單的論述了pc並口協議（ epp ）與dsp之間的通信方法、 cpld模塊邏輯控制應用和arinc429的通訊規范的基礎上，給出了基於dsp的arinc429通訊介面的設計方案:對通訊板中各模塊的功能和應用以及構成數據轉換主體的總線介面晶元hs - 3282的工作原理做了說明;介紹了本設計所用的dsp和cpld的功能概況;詳細敘述了通訊板介面模塊的硬體結構設計，其中，對數據緩沖電路、數據傳輸速率選擇電路、邏輯控制電路等各關鍵點做了重點介紹;具體闡述了軟體設計思想及流程圖，包括軟體的基本要求和功能的設計與實現;接著從埠譯碼單元、 i / o通道、電平轉換電路等方面進行了介面模塊的軟、硬體調試;最後，給出了測試結果，對研製工作做了總結，對本設計的優缺點各做了評述。
  9. They are vref, iref, current matrix, switch matrix, latch and decoder. vref, current matrix, switch matrix and decoder are the key parts in dac design. the errors caused by them are analyzed and suppressed in the paper

    其中，基準電壓電路，電流源陣列、開關陣列和譯碼電路是整個設計的重點和難點，它們設計的好壞直接影響著dac電路特性的優劣。
  10. This is the core of the issue. in this section we designed the cells of the dac, including the decoder circuit, bandgap reference voltage circuit, current source circuit and switched circuit etc. the fourth chapter the simulations of circuit and errors of the dac are discussedi, so the simulation waveforms are plotted on the paper and we must take the error corrections and minimize ways

    對于整個d a轉換器的具體結構和電路設計放在第三章，這也是本文的核心之處，對d a轉換器的整體電路及主要電路單元如：數字譯碼電路、帶隙參考電壓源電路、電流源產生電路、差分電流開關電路等進行詳細地分析和設計。
  11. The whole circuit includes memory array, decode, sense amplifier, data in - out circuit and pre - charge circuit

    電路包括存儲陣列、譯碼電路、敏感放大器、數據輸入輸出電路，預充電電路等部分。
  12. The input data of the multiplexing adopts 8 channels with the speed of 2mb / s, and those of the last two channels are " 0 " and " 1 " respectively, in order to improve the transimision effeciency and deminish the complexity of encode and electronic circuit concerned, furthermore, it makes the synchronous signal acquisition more easier

    數字復接中採用八路2m口數據輸入，其中后兩路採用直接輸入「 0 」碼或「 1 」碼的方法，提高了信息傳輸的有效性，便於提取幀同步碼，降低了編譯碼過程的復雜性，同時也降低了系統的電路復雜程度。
  13. An application of logic devices able to program to the decoding circuit

    可編程邏輯器件在譯碼電路中的應用
  14. The paper is completed research of measurement and control system based on dsp under technology. the paper is designed a card with the data - collection conversion and control by adopting mainly tms320f240 among the dsps as kernel processor, with peripheric a / d and d / a circuit epm7128 ' s decode and latch circuit and isa interface circuit

    本論文主要是採用數字信號處理器dsp中的tms320f240作為核心處理器，結合外部的模數轉換和數模轉換電路、可編程邏輯器件epm7128的地址譯碼和鎖存電路和isa介面電路，設計了集採集、轉換、控制於一身的isa卡。
  15. It has been playing an important role in equipping all kinds of arms and services for campaigns, tactical exercises and emergent actions etc. based on the detailed analysis of the exchange ' s architecture and implementing, this thesis points out some disadvantages of the device, such as too many absolute components, not very high enough reliability and security, very large size and weight, operating and maintaining difficultly. considering low power requirement and man - machine interface optimizing design at the same time, the thesis come up with an integrated design scheme to the previous device based on " mcu + cpld / fpga architecture " : ( 1 ) signal frequency dividing, timing frequency producing, 20 customers " led states controlling are implemented in cpld ; ( 2 ) decoding, latching data and controlling signals are implemented in cpld by bus interface between mcu and cpld ; ( 3 ) chip selecting principles and mcu idle mode design are completed under the consideration of low power requirement ; ( 4 ) operation by chinese lcd menus is adopted in the man - machine interface

    本項目以該交換機為研究對象，在詳細分析原設備的系統結構和功能實現方式的基礎上，指出該機型在使用過程中存在技術相對陳舊、分立元件過多、可靠性和保密性不夠、體積大、重量大、維修困難等問題，同時結合系統的低功耗需求和優化人機介面設計，本文提出基於「單片機+ cpld fpga體系結構」的集成化設計方案：在cpld中實現信號音分頻和計時頻率生成電路、 20路用戶led狀態控制電路； cpld與單片機以總線介面方式實現譯碼、數據和控制信號鎖存功能的vhdl設計；基於低功耗設計的器件選型方案和單片機待機模式設計；人機介面的lcd菜單操作方式。
  16. Audio codec requirements for the provision of bi - directional audio service over cable television networks using cable modem

    使用電纜數據機通過有線電視網路提供雙向音頻服務的音頻編碼譯碼器要求
  17. The circuit design mainly includes interface designs, such as address coding circuit, memory, human - machine, ad converter, the power, etc. the pcb was protracted and tested

    電路設計主要包括譯碼電路設計、存儲器介面電路設計、人機介面電路設計、 ad轉換器電路設計、數控恆流源介面設計等。
  18. The hardware system includes power supply circuit, clock reset circuit, jtag model building circuit, decoding circuit, memory interface circuit, man - machine interface circuit and numeric control constant - current source interface circuit

    硬體系統主要包括電源電路、時鐘復位電路、 jtag模擬介面電路，譯碼電路、存儲器介面電路、人機介面電路、 adc轉換電路和數控恆流源介面等。
  19. In this paper, the methodology and implementation with hdl of design based reconfigurable architecture are discussed in detail, which includes the implementations of algorithms circuit, register file with controllable node, decoder, interface and main controller. from the introduction of design process of every module circuit, we can see easily some general feature of vlsi design with hdl

    在此基礎上詳細討論了基於可重組體系結構的密碼晶元設計方法和各電路實現的結構圖，包括演算法電路、可控節點寄存器堆、譯碼電路、介面電路和主控模塊電路等。通過對各個模塊設計過程的介紹，闡明了使用hdl語言設計超大規模集成電路的一般特點。
  20. The down - up design includes the researches of decoder schematics, controller schematics, pipeline schematics, bus schematics, stack schematics and interrupt schematics. the thesis content and outcome of research are beneficial to the design of a cpu design project. at the same time, these contents are beneficial to the design of a microcontroller

    整個正向設計由於採用了簡化的措施，還存在一些不足，因此從逆向設計的角度，研究了pic微控制器晶元中處理器的電路實現結構，主要包括譯碼電路和控制器電路的實現結構，流水線電路的實現結構，處理器內總線的實現結構，以及堆棧和中斷電路這些與處理器電路有密切相關性的子電路單元。
分享友人
分享到 Line

分享到臉書