鎖相環路 的英文怎麼說

中文拼音 [suǒxiānghuánlù]
鎖相環路 英文
loop, phase-locked （pll）
  • 鎖 : Ⅰ名詞1 （安在開合處使人不能隨便打開的器具） lock 2 （姓氏） a surname Ⅱ動詞1 （上鎖） lock up 2 ...
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  1. Contrapose to the instability of the third - order charge - pump pll system, the loop optimization method is employed in system level design to decide the bandwidth and phase margin, therefore the loop bandwidth locates at the maximum phase margin to guarantee the stability of the system. according to tsmc 0. 35 m sige bicmos model, the sub - circuits in the designed pll and the whole system are simulated and verified by the cadence spectre

    5 .根據tsmc0 . 35 msigebicmos工藝模型，利用cadencespectre模擬軟體對所設計的電荷泵鎖相環路中各個模塊及整個系統進行了模擬模擬，模擬結果顯示，在1 . 5v電源電壓下，頻率為200mhz的參考輸入信號，輸出中心頻率為800mhz ，分頻電路採用4分頻，環路帶寬為10mhz ，捕獲時間大約為0 . 92 s ，功耗大約為15mw ，達到了設計指標。
  2. In the next place, by studying the change of the resonant frequency of the whole system, this paper designs the circuit to track the resonant frequency of the system by cd4046 mainly. at the same time, in order to improve the efficiency and get better dynamic capability of the converter, we choose pll and fuzzy control after comparing the pll circuit, fuzzy circuit and pll ? fuzzy control circuit. in the end, this paper brings forward the control blue print to realize the drive control circuit of the high frequency converter, using the dsp chip as the key part to realize four routes of pwm drive pulses with dead band of the control system

    其次，通過對整個系統諧振頻率變化的分析和研究，設計了以鎖相環cd4046為核心的鎖相環控制電路，同時，在綜合比較鎖相環控制、模糊控制以及模糊控制和鎖相環復合控制三種控制演算法的基礎上，進行了系統模擬，得出採用復合控制可使跟蹤電路既具有鎖相環路較好的穩態性能，又擁有模糊控制較好的動態性能，系統魯棒性能好，同時也提高了逆變器的效率。
  3. Monitor apparatus can measure valid value of three phase voltage and current, power factor, three phase disequilibrium, instant flecker of short time and harmonic without twenty, degree and harmonic distortion total. the paper are laid on the following. ( 1 ) master plan and function of circuit, ( 2 ) hardware design including circuit and principle of a / d conversion, phase lock, liquid crystal display and keystroke and so on, ( 3 ) design of system software including digital filtering, fft, a / d conversion and monitor interface of pc, ( 4 ) system test

    監測儀能夠完成包括三相電壓、三相電流的有效值、功率因數、三相不平衡、電壓短期閃變、以及20次內的諧波、諧波相位、諧波失真總量等的測量。論文重點介紹了以下幾部分： （ 1 ）電路的總體設計和功能； （ 2 ）硬體設計，包括a d轉換、鎖相環、液晶顯示和按鍵輸入等原理和電路。 （ 3 ）系統軟體設計，包括a d轉換、 fft 、數字濾波等程序的原理和演算法以及上位機監控界面的設計； （ 4 ）系統測試。
  4. Design of hardware consists of three pll loops, micro wave sample mixer, fractional - n frequency divider

    硬體電路包括三個鎖相環，取樣混頻器，分數分頻器的設計等。
  5. In this thesis, firstly, we put forward a new algorithm of the synchronization of carrier reference phase, that is to use the curve synthesizing with the general digital carrier phase looper to have an estimation on carrier frequency within 10 ms so as to meet the need of meteor burst communication. we have done some simulations to get the performance of carrier frequency estimation using two modulation modes ( 16qam and 4 - qpsk ), and had some test on the carrier phase looper in conditions when using different baud rate transmission and when the baud tuning have windage

    我們對兩種正交調制方式（ 16qam和4 - qpsk ）進行了模擬工作並給出了模擬結果，同時討論了碼元同步定時誤差對鎖相環路工作的影響並根據流星通信中使用變速率傳輸時鎖相環路的載波同步性能進行了測試；然後在基於軟體無線電思想的數字處理平臺（該數字處理平臺實現了中頻數字化）上用dsp軟體完成了載波的相位跟蹤。
  6. In this paper, a clock recovery system that based on phase control technology is studied

    本文設計的鎖相環路是基於相位控制技術的時鐘恢復系統。
  7. The clock recovery block of usb2. 0 transceiver macrocell consists of phase locked circuit, such as pll and dll ( delay locked loop ). this block use external crystal 12mhz sin signal to produce 60mhz, 120mhz, 480mhz clock signal, and can recover colock signal form date wave. it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2. 0 specification.

    目的是用鎖相環電路? pll和dll （延遲鎖相環）實現usb2 . 0收發器宏單元utm的時鐘恢復模塊。其中pll環路構成的時鐘發生器將外部晶振的12mhz正弦信號生成60mhz 、 120mhz 、 480mhz等本地時鐘信號。 dll環路依據本地時鐘信號對外部數據信號進行時鐘恢復。
  8. Then we uses the scheme that has the variable gain based on the kalman filtering model realize two steps phase - locks ring circuit track technology, this kind has the advantage that when changed the gain the digital phase - lock link to be allowed simultaneously to realize the fast capture and the reliable track, the simulation analyzes its capture performance

    模擬結果表明，自編碼直擴通信系統的編碼捕獲性能具有可行性。採用基於卡爾曼濾波模型實現具有可變增益的二階鎖相環路的跟蹤技術，這種具有時變增益的數字鎖相環可以同時實現快速捕獲和可靠跟蹤，其捕獲性能要比傳統數字鎖相環改善很多。
  9. With the phase - noise model of the phase loked loop ( pll ) and the analysis of spur characteristic of fractional - n frequency synthesizer using - ? modulating technology, the scheme of pll with mixer + quadrupler is confirmed as a result

    文中，通過建立鎖相環路的相位噪聲模型，並分析了使用- ?調制技術的分數頻率綜合器的雜散性能，以此二者為理論依據完成了毫米波頻率源合成器的基本方案? ?鎖相混頻環+倍頻器方案。
  10. Through the research of direct digital synthesizer ( dds ) used as a divider in phase lock loop ( pll ), a frequency synthesizer with small frequency resolution ratio and high purity frequency spectrum can be realized

    摘要通過對直接數字合成器在鎖相環路中作為分頻器應用的研究，使頻率合成器可以在實現超細頻率解析度的同時達到高的頻譜純度。
  11. The basic operation principle of phase - locked frequency synthesizer and the type of circuits are expatiated systematicly in this paper. the principle of operation on sampling phase detector and some characteristics including the linear tracking and phase noise in phase loop circuits are analyzed deeply. the research is emphased on the theory and design method of circuits in the sampling phase - locked frequency synthesizer. then, the expansion capturing circuit is analyzed and designed for better performance of capturing loop circuits. at last, the loop filter is also analyzed and contrived taking account of effection of additional phase shift by the sampling - holder. the general research on the theory and technology of sampling phase lock in the paper will make a basement for the development of new product

    本文系統的闡述了鎖相頻率合成器的基本工作原理及電路類型；較深入地分析了取樣鑒相工作原理及電路、鎖相環路的線性跟蹤特性和相位噪聲特性；重點對取樣鎖相頻率合成器電路理論和設計方法進行了研究；為了改善環路的捕獲性能，對擴捕電路進行了分析和設計，並用wewb32軟體對電路進行了模擬；考慮到取樣保持器的附加相移影響，對環路濾波器進行了分析和設計。
  12. In this paper, a pll frequency synthesizer working in l band is researched. at fist, we review the basic of phase lock loop and it ' s constituent part. after that the basic conception and design method of pll frequency synthesizer was introduced, especially introduced the charge pump pll frequency synthesizer in detail

    本文是採用鎖相原理設計的l波段頻率合成器，首先對鎖相環路的工作原理和基本組成部分進行了簡單的介紹，然後介紹了鎖相頻率合成器的原理和設計方法，主要介紹了目前小型頻率合成器產品中使用最廣泛的由電荷泵數字鑒頻鑒相器和無源環路濾波器構成的頻率合成器。
  13. The phase noise in microwave receiver and the measured parameter of source frequency instability are described in this paper, and the technology of frequency - synthesizing and theory of phase locked loop ( pll ) are also briefly introduced

    摘要闡述了微波接收機中的相位噪聲概念及本振源頻率不穩定度的實際測量參數，並簡要介紹了頻率合成技術和鎖相環路工作原理。
  14. The components used in the system project are detailed analyzed. all the parts contributed to phase noise are discussed as emphases. this millimeter wave frequency synthesizer has better phase noise and wider band

    本文詳細分析了本系統方案及其特性，並對其中用到的鎖相環路各部件及其對系統相位噪聲性能的影響作了重點討論。
  15. 3. the methods to improve and enhance the performance parameters of frequency synthesizer, such as phase noise and frequency stability, are discussed detailly and deeply through the linear phase model of pll which is using to implement the

    3 .利用鎖相環路的線性相位模型，詳細討論了利用鎖相環進行頻率合成時，頻率合成器的主要性能參數如相位噪聲和頻率穩定度的改進方法。
  16. Through the combination of inverter circuit and pll circuit, the process of frequency - tracking is described, and the experimental waves can be reflected perfectly. this provides some experience for the designing and debugging of electrical source

    並將鎖相環路與主電路結合起來，觀察到頻率跟蹤的過程，很好的反映了實際波形，為今後該類電源裝置的設計調試提供了良好的前期準備。
  17. We design the digital phase - locked loop applying the method designing digital circuitry from the top down. we design the circuitry by the vhdl in the maxpulsii software environment. we validate the circuitry function in the emulator

    採用自頂向下的數字電路設計方法設計全數字鎖相環路，在maxplusii設計環境下採用vhdl語言、 ahdl語言等設計實現數字鎖相環，並通過計算機模擬證實其正確性。
  18. At last we introduce the realization of all the parts, the problem in the circuit design and the measured data. the results show that the designed system has met the requirement. in this dissertation, direct digital synthesis technology has been used in the phase - locked frequency synthesizer, which can make full use of the characteristics of direct digital synthesis technology such as flexible output wave shape and continuous

    本課題將直接數字式合成技術用於鎖相頻率合成器中，該方法將直接數字合成的特點，如輸出波形靈活且相位連續、頻率穩定度高、輸出頻率解析度高、頻率轉換速度快、輸出相位噪聲低、集成度高、功耗低、體積小等與鎖相環路的頻帶寬、工作頻率高、頻譜質量好等優點有機的結合起來，從而在寬帶的條件下實現了比較好的雜散性能和相噪。
  19. This paper introduces the principle of phase - locked loop and analyzes the performance characteristics of pll chip adf4106 which has wide bandwidth and low power consumption. and then introduces the design method of a kind of low phase noise frequency synthesizers which uses single chip processor to control the chip. the application supplies a good design method for high frequency synthesizer

    介紹了鎖相環路的工作原理，分析了低功耗寬帶集成鎖相環晶元adf4106的工作特性，並介紹了一種利用單片機控制該晶元的低相位噪聲頻率合成器的設計方法，討論了環路濾波器的設計，為高頻頻率合成器的設計提供了很好的思路。
  20. On basic of researching the principle of phase locked loop, this article analyzes the output signal whose noise characteristics depend on the each part of pll, and designs a scheme to realize the frequency synthesizers using the high performance chips with integrated prescalers and phase detectors. the visualized circuit structure is given in this paper

    本文在研究鎖相環路基本原理的基礎上，分析了鎖相式頻率合成器電路中各部件對環路輸出信號噪聲性能的影響，設計了以一個高性能的集成鎖相環頻率合成器晶元為基礎實現頻率合成的方案，並給出了具體的電路形式。
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