鎖相環鑒頻器 的英文怎麼說

中文拼音 [suǒxiānghuánjiànbīn]
鎖相環鑒頻器 英文
phase locked loop frequency demodulator
  • : Ⅰ名詞1 (安在開合處使人不能隨便打開的器具) lock 2 (姓氏) a surname Ⅱ動詞1 (上鎖) lock up 2 ...
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  • : 名詞1. (器具) implement; utensil; ware 2. (器官) organ 3. (度量; 才能) capacity; talent 4. (姓氏) a surname
  1. For digital audio encoding and decoding modules, delta - sigma modulation is introduced and audio data, preambles with accessorial data are multiplexed according to the digital audio interface standard ; for carrier wave, pll frequency synthesizer is used ; for frequency modulation, voltage control oscillator is taken ; for demodulation, pll frequency discrimination is adopted

    調制方式,並按照數字音介面標準對音數據、同步字和附加信息進行通道復用;對于載波信號,採取率合成技術手段;對于率調制,採用壓控振蕩;對于解調電路,採取電路。
  2. The basic operation principle of phase - locked frequency synthesizer and the type of circuits are expatiated systematicly in this paper. the principle of operation on sampling phase detector and some characteristics including the linear tracking and phase noise in phase loop circuits are analyzed deeply. the research is emphased on the theory and design method of circuits in the sampling phase - locked frequency synthesizer. then, the expansion capturing circuit is analyzed and designed for better performance of capturing loop circuits. at last, the loop filter is also analyzed and contrived taking account of effection of additional phase shift by the sampling - holder. the general research on the theory and technology of sampling phase lock in the paper will make a basement for the development of new product

    本文系統的闡述了率合成的基本工作原理及電路類型;較深入地分析了取樣工作原理及電路、路的線性跟蹤特性和位噪聲特性;重點對取樣率合成電路理論和設計方法進行了研究;為了改善路的捕獲性能,對擴捕電路進行了分析和設計,並用wewb32軟體對電路進行了模擬;考慮到取樣保持的附加移影響,對路濾波進行了分析和設計。
  3. In this paper, a pll frequency synthesizer working in l band is researched. at fist, we review the basic of phase lock loop and it ' s constituent part. after that the basic conception and design method of pll frequency synthesizer was introduced, especially introduced the charge pump pll frequency synthesizer in detail

    本文是採用原理設計的l波段率合成,首先對路的工作原理和基本組成部分進行了簡單的介紹,然後介紹了率合成的原理和設計方法,主要介紹了目前小型率合成產品中使用最廣泛的由電荷泵數字和無源路濾波構成的率合成
  4. Then according to the emphasis of the design, went deeply into the theory of pll frequency synthesizers widely used, described pll ’ s working principle, structure and several types in detail, and made research and analysis of pll frequency synthesizers ’ phase noise, including the effect of the active loop filter on the phase noise, and give some methods to make improvement as well, such as changing loop filter form, reducing divide number, and increase phase detector frequency, etc. then paper introduced the principle character and phase noise analysis of direct digital frequency synthesizer ( dds ) and injection phase lock circuit, which are also important circuits in the design

    論文首先對幾十年率合成的發展進行概述,而後針對本次設計的重點,對應用較為廣泛的率合成理論進行了深入的探討,詳細介紹了的工作原理、組成結構和類型,並對率合成噪特性進行了研究分析,包括有源路濾波對于噪的影響,提出了改善位噪聲的幾點措施:改善路形式、降低分數、增大率等。接著介紹了直接數字率合成( dds )和注入電路的原理特點以及噪分析,它們也是本次設計的重要電路。
  5. The thesis describes a prototype fractional frequency synthesizer which is supported by a project granted by the ministry of science and technology of pr china. firstly, based on the principle of pll, this paper briefly describes three basic pll components : phase detector ( pd ), low pass filter ( lpf ), voltage controlled oscillators ( vco ), analyzes the linearized pll and summaries the transfer functions of third - order pll with ideal intergrator filter respectively. based on a microwave vco, the single point frequency pll frequency ranging from 2. 2 to 2. 5ghz is developed

    首先,從的基本理論、原理出發,分析了中的三個基本部件:路濾波和壓控振蕩,此後,針對線性化進行了分析,研究了在使用比例積分濾波時,三階路參數計算;在電路實現時選用了lmx2353 ,在此基礎上,完成了2 . 2 ~ 2 . 5ghz范圍內的小數率合成設計。
  6. But its performance is as same as common pll at a 5v voltage. so the pll performance is better than other plls at a 5v voltage, especially in power consumption and frequency. finally, the improved pll circuit used in the frequency synthesizer is composed of the improved vco, phase / frequency detector and charge pump. hspice simulation results show that the pll performance is better than other plls implemented by other vco in the same cmos technology

    綜合以上的研究與設計,本文用所改進的壓控振蕩、無死區及電荷泵電路組成了用於率合成的電路,並對此電路進行整體設計及模擬,結果表明其在定時間、率范圍、輸出位抖動及功耗方面具有較好的性能,且對提高率合成的整體性能有一定的作用。
  7. The fourth, mainly talk about the phase noise in the pll, and discuss the specific affect on out put phase noise caused by different components in frequency synthesizer, such as mixer, amplifier, multipler, divider, oscillator, phase detector etc. the last part is about how to choice the natural frequency of pll in order to get the better performance in phase noise

    第二章從的基本原理出發,介紹了的幾個基本部件:?路濾波和壓控振蕩,對線性化進行了詳細的分析,對數字做了詳細的介紹,分析了位噪聲模型,討論了綜中的混
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