circuit complexity 中文意思是什麼

circuit complexity 解釋
電路復雜性
  • circuit : n 1 （某一范圍的）周邊一圈；巡迴，周遊；巡迴路線[區域]；迂路。2 巡迴審判（區）；巡迴律師會。3 【...
  • complexity : n. 1. 復雜性，復合狀態。2. 復合物；復雜的事物[情況]。
  1. The sy - stem had different requirements on time sequence in high - speed clock and low - speed clock situations, which resulted in the complexity of the sequential circuit

    在高速時鐘和低速時鐘的情況下，系統有不同的時序要求，這就決定了時序電路的復雜性。
  2. Smart antenna has two critical tasks, one is to filter the uplink signals, and the other is to form the downlink beam, and we need adaptive algorithm and digital signal processing ( dsp ) technology to fulfill these work. adaptive algorithm is one of the most important technologies of smart antenna, and it determines smart antenna ' s speed to the wanted to signal and the complexity of the circuit of the communication system

    自適應演算法是智能天線的核心技術之一，它決定著智能天線對來波信號響應的速率和系統實現電路的復雜程度，系統需要針對各種通信環境來選擇合適的演算法，也可以採用演算法分集的方法來使整個系統工作在最佳狀態。
  3. With the rapid development of the semiconductor process and relevant technology, beyond the traditional integrated circuit, system - on - a - chip ( soc ) is coming up. it consists of a lot of intellectual property ( ip ) blocks and embedded processors, which require a piece of embedded software code to be composed. with design complexity beyond the traditional chips, verification difficulty is growing up

    系統晶元是隨著集成電路的發展而出現的新一代晶元，在系統晶元的設計中大量採用ip核復用技術，系統晶元中還包含有嵌入式的處理器，因而需要同時設計嵌入式的軟體程序，其設計復雜度遠遠高於傳統的ic晶元。
  4. The inversionless bm algorithm in rs decoder is implemented with serial mode, which avoids the inversion computation and only needs 3 finite - field multipliers. thus, the complexity of hardware implementation has been mostly reduced. a 3 - level pipe - line processing architecture is also used in the hardware and the coding circuit in rs coder is optimized by using the characteristics of the finite - field constant multiplier

    Rs解碼器的設計採用無逆bm演算法，並利用串列方式來實現，不僅避免了求逆運算，而且只需用3個有限域乘法器就可以實現，大大的降低了硬體實現的復雜度，並且因為在硬體實現上，採用了3級流水線（ pipe - line ）的處理結構。
  5. Secondly, the encoder circuit of quasi - cyclic which can realize low encoding complexity are designed and implemented. three encoder circuit are designed respectively with feed shift - registers and logic gates : sraa - based serial qc - ldpc encoder ; sraa - based parallel qc - ldpc encoder ; two - stage qc - ldpc encoder

    採用反饋移位寄存器與邏輯門設計了三個典型的編碼器電路:基於sraa電路的串列準循環ldpc碼編碼器;基於sraa電路的并行準循環ldpc碼編碼器;二階編碼電路。
  6. The hip interface of dsp is set to universal i / o port, / bio used as handshake signal line, it can transmit merger result to the adjudicate dsp high speed. thus it simplified the complexity of the interface circuit

    將dsp的hpi介面設置為通用fo埠， / bio作為握手信號線，使融合結果能夠高速地傳輸給判決ds屍，從而簡化了介面電路的復雜性。
  7. On introducing a new method of complexity measure analysis, the authors manage to inspect the circuit fault status by analyzing synthetic signal

    作者引入了一種新的復雜性分析的方法，利用綜合性信號監測電路故障狀態。
  8. In deep sub - micron technology, the scale of integration and the degree of complexity of circuit increase rapidly, it is necessary and feasible to adopt non - manhattan model for detailed routing in vlsi physical design. aiming at the current pop point a novel non - manhattan otc router is proposed in section 4. according to the routing algorithm of channel area the new otc router selects nets on cell by using net segment valid controlling column technology, deep searching to column density technology and utilization of vacant terminals technology

    結合通道區域所用非曼哈頓布線演算法的特點，通過採用線網段有效控制列技術、列密度深度探測技術及空端利用技術對單元區可布線網進行有效選擇，成功地實現了該非曼哈頓單元上布線演算法，並將其應用於一些經典的benchmark中，和目前文獻中現有演算法相比取得了更優的布線結果。
  9. The fault diagnosis of the analog circuits is an advanced synthesis intercrossed subj ect, which is an application technology absorbing the new theory, technology and method in other subjects and fields. in the past 40 years, it has developed a great deal of theory and approaches. but the approaches are limited to deal with fault diagnosis because of the variety and complexity of the analog circuits, especially the large - scale analog circuits with the tolerance or the soft fault. artificial neural networks ( ann ) which have been one of the most active research areas recently can be contributed to solve problems in various practical fields. in this paper, analog circuit fault diagnosis approach based on pattern recognition, and ann is expatiated

    模擬電路故障診斷是一門不斷發展中的綜合交叉性學科，是在不斷吸收其它學科和領域的新理論、新技術和新方法的基礎上向前發展的一門應用技術。雖然經過了四十多年的發展，也已經形成了一系列的診斷理論和方法，但由於模擬電路特別是有容差的大規模模擬電路故障的多樣性和復雜性，使得可用於診斷容差模擬電路的故障和大規模模擬電路軟故障的方法還十分有限。人工神經網路理論近年來取得了快速發展，已開始在各個研究領域廣泛應用。
  10. The quantum gate array is the natural quantum generalization of acyclic combinational logic " circuit " studied in conventional computational complexity theory. in 1995, barenco showed that almost any two - bit gate is universal, so building a feasible two - bit logic gate is the first step to engineer a quantum computer. in principle, the quantum bit can be carried by any two states system

    在眾多的量子計算機模型中目前討論最廣泛的是量子計算機門組網路模型，量子計算機門組網路模型是經典計算機門組網路結構的量子推廣，它是根基於barenco等人所證明的「一個兩比特受控操作和對單比特進行任意操作的門可以構成一個『通用量子邏輯門組』 」之上的。
  11. However, as time - to - market pressures and chip complexity grow, current design tools and methodologies are inadequate for developing million - gate socs from scratch. reuse of pre - designed and pre - verified circuit modules, known as ip ( lntellectual property ), is the most promising method to bridge the gap between large gate number and designer productivity

    但由於soc的規模非常龐大，很少有單個公司能夠承擔整個soc的開發和維護，加之面市時間（ time - to - market ）的巨大壓力，人們逐漸認識到基於預先設計好的ip （ intellectualproperty ）進行soc的集成是提升soc設計效率的非常有效的方法。
  12. Based on the analysis of the paper, we can draw the conclusion that this device has several issues to be solved to put into use, such as low filtering capacity, large bulk and area the device occupies, complexity of connection, and the hazard of ferro - resonance existing when switching without disconnecting the circuit of the step - up transformer

    經過分析發現，這種補償方案存在一些問題，如濾波能力低，補償裝置體積大，佔地面積多，接線復雜；並且如果在投切過程中不將升壓變壓器高壓側迴路斷開，存在著發生鐵磁諧振的危險。
  13. The input data of the multiplexing adopts 8 channels with the speed of 2mb / s, and those of the last two channels are " 0 " and " 1 " respectively, in order to improve the transimision effeciency and deminish the complexity of encode and electronic circuit concerned, furthermore, it makes the synchronous signal acquisition more easier

    數字復接中採用八路2m口數據輸入，其中后兩路採用直接輸入「 0 」碼或「 1 」碼的方法，提高了信息傳輸的有效性，便於提取幀同步碼，降低了編譯碼過程的復雜性，同時也降低了系統的電路復雜程度。
  14. An improved high - resolution current - mode sorter is presented. its structure complexity is o ( n ), which is crucial to the expansion of its size, and its dynamic range is large. only one clock signal and one reset signal are needed. no biasing signal is required. the operation point is constructed according to the input current, so it is self - adaptive, which is very important for an all - purpose component. in average value circuit, subtraction circuit, winner - take - all ( wta ) circuit and control circuit, it has good performance even at a large input current. this sorter has high precision, high resolution and low power, as has been proved via hspice simulation. it can be implemented in the standard digital cmos technology and widely used in many fields, so it is of great value in applications

    提出了一種改進的高精度電流型排序電路.它的結構復雜性僅為o （ n ） ，便於擴展;動態范圍大;它是自適應的，工作點由輸入電流確定，故不需要偏置信號，這對作為通用器件使用的排序電路來說是很重要的.通過利用平均值電路、減法電路、 wta電路和控制電路，可以使該電路在大輸入電流下依然保持高性能. hspice模擬表明該電路具有高準確性、高精度、低功耗的特點.它能用標準數字cmos工藝來實現，可以被應用於很多領域，具有很高的應用價值
  15. And one of the basic difficulties lies in the complexity of the fault models in the analog system since both the input stimulus and output response are continuous variables, and the parameters in the circuit components are also continuous too

    難點之一是模擬電路中的輸入激勵和輸出響應都是連續量，電路中元件的參數通常也是連續的，所以模擬系統中的故障模型比較復雜，難以作簡單的量化。
  16. Utilizing the interface, all most aspects of chua ' s circuit, including circuit ' s parameters, initial conditions, eigenvalues, vector field, movement track, and so on, may be fully and directly reflected. on the one hand, it solves existing situation of no - directly perceived nature and complexity in researching all aspects of chua ' s circuit ; on the other hand, investigators can still more conveniently study the circuit

    4 ）設計了一個用戶界面，可對chua混沌電路的參數、初始條件、特徵值、矢量場、運動軌跡等各個環節進行全面、直觀的反映，解決了目前研究chua混沌電路各環一竹的不直觀性和計算電路參數的復雜性，可使研究者更進一步方便的研究電路。
  17. Reactive power are calculated using the new algorithm. on the basis of analyzing different kinds of control strategies of var compensation, the paper applies the criterion of voltage and var to control switching and illustrates a improved mode of switching capacitor which can prevent the switched - capacitor from the impacting of instantaneous rush currents by means of zero - crossing triggering of scr components, and can realize auto - tracking var and auto - switching shunt capacitor bank. initial operating parameters are stored in information flash memory of the mcu using flash self - programming technique in order to decrease complexity of the circuit and improve stability

    高壓智能無功補償控制器以flash型16位單片機msp430f149為控制核心，採用了一種相角實時測量的新演算法，並在此基礎上計算出了功率因數、有功和無功，減少了運算量提高了精度；在分析了各種無功補償控制策略的基礎上，以母線電壓和無功功率復合判據控制投切，並提出一種改進的電容器投切方式? ?暫態投切控制晶閘管過零觸發，避免了電容器投切時的電流沖擊；穩態運行時接觸器替代晶閘管，實現無功補償的自動跟蹤和電容器的自動投切，解決了投切時的暫態電流沖擊和穩態時可靠運行的難題；控制器的原始運行參數採用flash自編程技術，將其保存在msp430f149片內的信息flash中，簡化了硬體電路，大大提高了系統的可靠性。
  18. Because multipath searcher and code tracking are accomplished on the hardware, the complexity of the circuit should be concerned

    同時由於多徑搜索和同步跟蹤是在硬體上進行處理，實現電路的復雜度也需要考慮。
  19. As the random structure of ldpc codes made it difficult to encoding in hardware and few mathematic methods has been found for analyzing these codes, many constructed ldpc codes were investigated to simplify encoding circuit and to reduce the complexity of analyses

    隨機構造的ldpc碼缺乏系統的分析理論，且編碼部分的硬體實現困難，成為ldpc碼應用的一個瓶頸，因此許多的結構化的ldpc碼被相繼提出，以簡化編碼的硬體復雜度和理論分析的難度。
  20. Sparse - tree architecture enables low carry - merge fan - outs and inter - stage wiring complexity. single - rail and semi - dynamic circuit improves operation speed. simulation results show that the proposed adder can operate at 485ps with power of 25. 6mw in 0. 18 - mu m cmos process

    具有代表性的并行前綴進位結構有kogge - stone樹brent - kung樹han - carlson樹和knowles樹等，一些高性能的加法器也由此被設計出來。
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