flip-and-flop 中文意思是什麼
flip-and-flop
解釋
雙穩態多諧振蕩器-
Was this another flip - flop from a man who has developed a reputation for confusing financial markets by sounding alternately hawkish and dovish
難道這是一個已經建立名聲的人再一次變換立場，為的是通過鷹派（激進）和鴿派（保守）兩種作風相交替來干預金融市場？ -
Just she and i. we had a great time. i took her to the restaurant in here southern california that is known for its delicious fish tacos, and the price is right for my budget. we made sure we wore a pair of flip - flop sandals and t - shirts, otherwise we would have been very overdressed
我帶她到南加州最好的餐廳，他們的食物是全球最好的，魚肉玉米片，世界上再沒有更好吃更優惠的魚肉玉米片去這地方，記得要穿人字拖鞋和汗衫，否則就會穿得太隆重了。 -
As an experiment of basic course in electronic technology, the project is based on domination principle of digital music player and integrates with the elementary application of multiplexer, flip - flop, counter and rom, which enables students to comprehend these knowledge fully along with acquaintance of technical application and promotes systematic understanding of basic notions, course content and advances the transformation from knowledge to ability
作為數字電子技術基礎課程的實驗內容，該方案設計以數字音樂播放的控制原理為切入點，結合了數據選擇器、觸發器、計數器和只讀存儲器的基本應用，使學生在充分理解這些知識點的同時了解一些工程應用背景，以形成對課程內容、基礎概念的系統認識，促進知識向能力的轉化。 -
Flip - flop is the core of sequential circuits, this dissertation designed a synchronous set - reset edge - trigged jk flip - flop based on rt quantum devices, the jk flip - flop has strong function and high speed, and also riches the types of flip - flops in quantum circuits
所設計的jk觸發器功能強，且與傳統的觸發器相比，基於rt量子器件的邊沿型jk觸發器具有量子器件的功耗低、速度快、電路簡單等特點。本文設計的jk觸發器豐富了量子電路中觸發器的種類，使得量子時序電路的設計更為靈活。 -
While sheetlet no. 1 was issued on 8 april 2003 and sheetlet no. 2 will be issued on 14 october 2003 as a run - up to the expo, tourism series no. 3 to 6 with each depicting a different facet of the expo theme will also be issued consecutively from the first day of the expo. a flip - flop stamp sheetlet will be issued to commemorate the opening of the expo on 30 january 2004
第一號小型張已於二三年四月八日發行，第二號將于同年十月十四日推出，而以不同的角度展示香港旅遊魅力的第三至六號小型張，則于郵博開幕日起逐日發行。香港郵政亦會於二四年一月三十日郵博首日發行一款疊影幻趣郵票小型張，慶祝郵博開幕。 -
In the meantime, the all sub - circuits are also designed and emulated carefully including inverter, rs type flip - flop, voltage reference circuit, error amplifier, voltage comparator, sawtooth - wave generator, pwm comparator, soft activation circuit and so on. as a result, all of the sub - circuits answer the requirements. this chip has taped out with the 0. 5um mix - signal process of csmc
本文利用cadenceeda集成電路設計工具、 spectres模擬工具，對集成電路內的各個模塊包括反相器、基本rs觸發器、基準電壓電路、誤差放大電路、電壓比較電路、鋸齒波振蕩發生電路、 pwm比較電路、軟啟動電路、驅動電路等進行了具體的設計和模擬，且達到了預先設定的指標。 -
In meantime, the all sub - circuits are also designed and emulated carefully including error amplifier, voltage reference circuit, voltage comparator, rs type flip - flop, soft - start circuit, sawtooth - wave generator, pwm comparator, current added circuit and so on
其次對控制器內部晶元的各個模塊誤差放大電器、自舉電流電路、電壓基準源、電流求和電路、 rs觸發器和驅動電路等模塊進行了具體的設計和模擬的邏輯功能做了解釋。 -
The whole circuit consists of a multiplier, an error amplifier, a comparator, a rs flip - flop, an and gate, and an inverter, etc. the electronic circuit simulator cadence is utilized to practice the detailed functional simulation of the general circuit and the subsystem circuits
整個電路由模擬乘法器、誤差放大器、比較器、 rs觸發器、與門和倒相器等基本單元電路組成，採用工作站上的大型ic設計軟體cadence進行模擬。 -
From the concept of triditional master - slave flip - flop, we propose a simplified positive edge - triggered flip - flop and prove the traditional positive edge - triggered flip - flop is the master - slave flip - flop designed based on basic flip - flop with single - rail input
並且從傳統主從結構觸發器出發，提出了簡化結構的維持阻塞型觸發器設計。針對數字電路中大量存在的冗餘現象，本文討論了冗餘抑制原理以及相應的冗餘抑制技術。 -
Circuit design is the basis of design of demultiplexer. speed, power and chip area are the main factors that should be considered in circuit design. every circuit structure has its merits and drawbacks, e. g. cmos logic family has a slower speed, but lower power, smaller area, scfl ( source couple fet logic ) family has a higher speed, but higher power, larger area. we should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors. flip - flop is the fundamental element of demultiplexer, setup time and hold up time are key factors, which influence the speed of circuit, thus the design aim is how to reduce them. in this thesis we place emphasis on the design of scfl latches
速度、功耗、面積是電路設計要考慮的主要因素，不同的電路形式具有不同的優缺點，如cmos互補邏輯電路功耗低，面積小，速度相對較慢； scfl （源極耦合fet邏輯）電路速度高，功耗和面積較大。所以要針對具體設計需要選用適當的電路形式或其組合結構，以滿足設計要求。觸發器是分接器的基本組成單元，建立時間和保持時間是影響電路速度的關鍵，所以減小建立時間和保持時間是觸發器設計的主要目標，本文著重介紹了scfl鎖存器的設計和優化方法。 -
As emphasis, we propose a new backward width - flrst search circuit partitioning method with flip - flop as core for synchronous sequential circuits. and then based on it, we develop a new circuit parallel tg algorithm
最後重點對電路并行方法進行了研究，提出了一種新的以觸發器為核且消除大功能塊之間反饋的寬度優先反向搜索同步時序電路劃分方法。 -
According to the redundancy in digital circuits, we investigate the diversified redundancy - restraining techniques for lower - power cmos circuits. to erase the redundant transition of the clock, the logic design of double - edge - triggered flip - flop is presented and applied in sequential circuit design
為消除時鐘信號的兀余跳變，提出了利用時鐘兩個方向跳變的雙邊沿觸發器邏輯發計並應用於時序電路設計中。 -
Detail specification for electronic components. semiconductor integrated circuit ct54h74 ct74h74 dual d - type positive edge - triggred flip - flop with preset and clear
電子元器件詳細規范.半導體集成電路ct54h74 ct74h74型雙上升沿d觸發器有預置端清除端 -
Base on the theory analysis of the superconducting rsfq digital circuit model, wrspice is used to do time domain simulation of superconducting rsfq digital circuit in this paper, and superconducting jtl, buffer, rs flip - flop, t flip - flop, and or gate are acquired
在超導rsfq數字電路模型的理論分析基礎上，論文中採用wrspice對超導rsfq數字電路進行時域模擬，得到了超導jtl傳輸線，緩沖器， rs觸發器， t觸發器，或門等基本邏輯單元電路以及電路參數。 -
Law and lawlessness are opposing polarities, and there is a point in which they cross and much like a teeter - totter, can flip flop from one extreme to the other
律法與無律法是對立的兩極，其中有一個重點是，它們彼此交叉就象蹺蹺板一樣，可以從一個極端來到另一個極端。 -
During the stamp expo, hongkong post issued a range of innovative philatelic products including " my stamp ", the hong kong 2004 stamp expo tourism series, the flip flop stamp sheetlet, commemorative and prestige collections of the " hong kong 2004 " stamp sheetlet and banknote, and of course, the hong kong attractions stamp sheetlet
于郵博期間，香港郵政發行了一系列別具創意的郵品，包括"我的郵票" 、香港2004郵票博覽會旅遊系列郵票小型張，疊影幻趣郵票小型張， "香港2004 "郵票及鈔票紀念套摺，當中亦包括這款"香港景緻"郵票小型張。 -
Is there value in this kind of research but i am glad to say that young chinese scholars today are very independent - minded, we should see fewer and fewer of those who flip - flop toeing the line
所幸的是，今天中國中青年學者獨立思考的能力很強，緊跟外交的需要而變調的學者今後會越來越少。 -
The main contribution of the thesis is seen as follows : aiming at the fault with slow speed and high power dissipation of the conventional phase - frequency detector, a high speed and low power dissipation phase - frequency detector is designed by modifying the structure of the single phase lock dynamic d flip - flop and adding the delay cell in the feedback loop to eliminate the phase detector ’ s dead zone effectively
論文的主要貢獻為以下幾個方面: 1 .針對傳統鑒頻鑒相器速度慢、功耗高的缺點，改進了單相時鐘動態d觸發器的結構，設計出了一種高速低功耗的鑒頻鑒相器，在反饋迴路上加入延遲單元，能有效的消除鑒相死區。 -
Design of double - edge - triggered dynamic flip - flop and its application
雙邊沿動態觸發器的設計及其應用 -
6. the theoretics of flip - flop anomalous property is perfected, and the oscillatory state of flip - flop is analyzed and the oscillatory frequency calculating equator is provided ; the self - adapting data synchronizer practical circuit with 0 error rate is designed, which can be used to resolve the problem of data synchronizing. the data synchronizer in common use is realized
6 、對觸發器的不確定性理論作了改進，討論了觸發器的非穩態過程，給出了一些計算觸發器振蕩頻率的公式，設計了自適應數據同步器實現電路，理論誤碼率為0 ，為解決數據同步問題提供了新思路，實現了常用數據同步器。
分享友人