memory system architecture 中文意思是什麼

memory system architecture 解釋
存儲系統結構
  • memory : n. 1. 記憶；記憶力；【自動化】存儲器；信息存儲方式；存儲量。2. 回憶。3. 紀念。4. 死後的名聲，遺芳。5. 追想得起的年限[范圍]。
  • system : n 1 體系，系統；分類法；組織；設備，裝置。2 方式；方法；作業方法。3 制度；主義。4 次序，規律。5 ...
  • architecture : n. 1. 建築學。2. 建築（樣式、風格）；建築物。3. 構造，結構；【自動化】（電子計算機的）架構，體系結構。
  1. Applying two perpendicular polarized light states and a no - light state to express information, this new theoretical system covers : a ) whole architecture constructed from light processing, light transmission, electric control and photoelectric input and output ; b ) various computing units mainly consist of liquid crystal element and polarimeter ; c ) light bus mainly consists of interlinkage optic valves ; d ) ternary memory formed from semiconductor memory ; e ) register formed from optic fiber ring ; and i ) huge - numeral management based on the new concept of calculating path and calculating channel

    這個理論包括：光處理、光傳送、電控制、綜合輸入輸出的總體結構；以液晶元件和偏振器為主的各類運算器結構；以互連光閥為主的光空間總線；以半導體存儲器為主的三值數據存儲器結構；以光纖環為主的寄存器結構；以算位、算道新概念為基礎的巨位數管理方案等。
  2. Once these changes ( dual mode, privileged instructions, memory protection, timer interrupt ) have been made to the basic computer architecture, it is possible to write a correct operating system

    一旦對一個基本的計算機體系結構完成了以上修改（雙模式、特許指令、內存保護、定時器中斷） ，就有可能寫出正確的操作系統。
  3. With turning the scale of asic ( appl ication specified integrated circuits ) to s0c ( system on chip ), which conunon1y is composed of mcu, specified function ip cores, memory, periphery interface etc, the ip reuse techno1ogy is very important in s0c design flow, which can realize the constructions of different levels components. the approach of configurable system, method and design f1ow for udsm ( u1tra deep sub micron ) asic, logic system design using hdl 1anguage, coding style, static and dynamic verification strategy are a1so presented in chapter 2. in chapter 3 we study the vlsi - - dsp architecture design, dense computation and high speed high performance digital signal processing unit structure, which includes high speed mac components and distributed arithmetic unit

    在工程設計方法及結構化設計和高層次綜合的研究中，介紹了在深亞微米工藝條件使用的方法和asic設計流程，討論了高層次綜合的核心如何從描述推出電路構成的設計思路，針對不同目標的設計技巧討論了採用hdl語言進行邏輯系統設計的方法，給出了用vhdl語言進行代碼設計時的規范和風格，在面向soc的驗證策略討論了動態和靜態的驗證技術，提出了進行單獨模塊驗證、晶元的全功能驗證和系統軟硬體協同驗證的整體策略。
  4. Cluster system is one of the hot spots in the research area of high performance computer, while system area network ( san ) that used to connect nodes is considered to be the key point in the cluster system the aims of this paper are to study dedicated high performance san network based on distributed shared memory architecture, and set up cluster system with high price performance ratio the main work and originalities in this paper list as followings : 1

    群機系統是高性能計算機研究領域的熱點之一，而用於連接群機系統內部結點的系統域網路（ san ）是群機系統研究的關鍵。本文在分佈共享存儲器結構的基礎上研究高性能專用san網路，構建高性能/價格比的群機系統。本文的主要工作和創新點如下： 1
  5. Abstract with the foundation of real - time, fault tolerant, standard compatibility, a standard for embedded real - time os was suggested, which included embedded os architecture, supported hardware, schedule management, memory management, inter ? process communication, timer performance, network support, file system, driver development and debug and so on

    摘要以與實時系統開發過程密切相關的實時性、故障容錯和標準兼容性等關鍵特徵為基礎，提出一套對嵌入式實時操作系統性能衡量的標準，涵蓋體系結構、硬體支持、調度管理、內存管理、進程間通訊、定時性能、網路支持、文件系統、驅動編程以及開發調試等關鍵特證。
  6. With the foundation of real - time, fault tolerant, standard compatibility, a standard for embedded real - time os was suggested, which included embedded os architecture, supported hardware, schedule management, memory management, inter - process communication, timer performance, network support, file system, driver development and debug and so on

    摘要以與實時系統開發過程密切相關的實時性、故障容錯和標準兼容性等關鍵特徵為基礎，提出一套對嵌入式實時操作系統性能衡量的標準，涵蓋體系結構、硬體支持、調度管理、內存管理、進程間通訊、定時性能、網路支持、文件系統、驅動編程以及開發調試等關鍵特證。
  7. In the dissertation ， we discribe the implementation of large capability video data acquisition system based on pci bus of computer 。 the system is composed of data acquisiton card and corresponding software 。 the data acquisiton card include two acquisition channels ， 8 - bit digitization at rates up to 13. 5mhz 。 frist ， the architecture of the video data acqusition system is studied 。 then ， the function and implementation methode of each module are introduced in detail 。 the control module of the video data acqusition card is implemented by using of the isp technology of cpld and vhdl programming technology 。 the a / d converter used assembler to implement the initialazation programe 。 and the double buffer technology is used for large capability data acqusition. because a contiously large memory is difficult to apply in windows operating system 。 finally we use broland c + + to introduced the devleoping procedure of drivers 。

    在實際的研製過程中，利用cpld的在系統可編程（ isp ）技術和基於vhdl語言的可編程邏輯器件設計技術實現了視頻數據採集卡的控制模塊。在視頻的a / d轉換模塊，用匯編程序模擬i2c總線對初始化a / d轉換晶元。針對大容量數據採集，採用了雙緩沖技術解決wndows操作系統下難以申請到大容童連續內存的間題。
  8. In the paper, the system architecture of the edbms based on the ems memory is pinpointed. those pivotal techniques in the development of the system, including the physical memorizer management, query process, data synchronization and other technology are further discussed

    在這個思想的指導下，本文重點考慮了基於內存的嵌入式數據庫管理系統的體系結構，採用了有效的物理存儲管理機制、查詢處理和數據同步技術，並對關鍵部分的實現方式進行了詳細討論。
  9. Even so, differences can arise in the areas that depend on the architecture, memory maps, threading, or some specific areas like system administration or natural language support

    即便如此，在那些依賴于體系架構的領域、內存映射、線程或一些特殊的領域（例如系統管理和自然語言的支持） ，它們之間還是有差異的。
  10. The on - chip memory performance of embedded systems directly affects the system designers decision about how to allocate expensive silicon area. a novel memory architecture, flexible sequential and random access memory fsram, is investigated for embedded systems

    而我們開展的一項研究驗證了一種新型低功耗的片外存儲器結構的性能潛力，即靈活的順序與隨機存取存儲器lexible sequential and random access memory ，簡稱fsram 。
  11. In the first part, this paper discusses the key problems in designing architecture of each component, which include why we choose partitioned regiater files, use 2 - way connected data cache with write - back strategy and add scratch - pad sram to original momory system, and how to identify their parameters. following that, a memory configuration based on the discussion above is presented

    本文首先介紹了dpc各個存儲器的設計和實現，詳細討論了寄存器文件分體結構的選擇並提出了寄存器文件參數配置的四條規律，介紹了數據cache容量及策略的權衡與選擇，闡述了scratch - padsram與cache並存的優勢。
  12. Following the architecture description of rtps middleware, two critical implementation issues are carried out : the first, object - oriented multi - threaded architecture. to avoid negative effect brought by the block, and to improve the realtime responsive ability of the system, we decouple the event processing from its transportation ; the second, pooled memory allocationjn order to decrease the time - and - space overhead due to dynamic memory allocation, thus to improve the dynamic performance of the realtime publish - subscribe system and the predictability of runtime end - to - end qos, we adopt the pooled allocation to change many dynamic system calls into one static system call and several user interface calls in fixed time

    通過將事件的輸送與處理解耦以避免阻塞所帶來的影響、改善系統的實時響應能力，通過面向對象的多線程並發以支持異步事件的實時並發處理並獲得系統結構上的靈活性；其二，池式內存分配。通過內存池分配方式將客戶的大量動態系統調用轉化為一次靜態系統調用和數次固定時間的用戶介面調用以減少動態內存分配的時空開銷，從而改善實時發布-訂閱系統的動態性能與提高其運行時端對端服務質量的（ end - to - endqos ）可預測性。
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