timing controller 中文意思是什麼

timing controller 解釋
定時控制器
  • timing : n. 1. 時間選擇。2. 定時，校時，計時，調速。3. 【自動化】同步；時限。
  • controller : n 1 管理人，主管人。2 （會計的）主計人，檢查員；〈英國〉（特指宮廷、海軍等的）出納官〈常作 comptr...
  1. Application of a new keyboard and display controller in timing equipment

    一種新型鍵盤顯示控制器在時統中的應用
  2. Its premise is pci bus specification and its sticking point is to analysis the function and architecture of pci bus controller. this dissertation finishes the design of pci bus controller, and it has also completed the function simulation of this module as well as timing simulation and a pcb card for test which prove it rightness at last

    通過本論文的研究，完成了pci總線控制器的設計，並且通過編寫測試激勵程序完成了總線控制器功能模擬，以及布局布線后的時序模擬，並設計了pcb實驗板進行了測試，證明所實現的pci目標控制器完成了要求的功能。
  3. Analyze the interpolation filter, timing - error detector and controller in loop of timing recovery detailedly

    詳細分析了定時恢復環路中的內插濾波器、定時誤差信號的提取、數控振蕩器。
  4. When its performace is determinate, the efficiency of the memory in a system depends on the design of the interface controller. this paper discuss the design of the nice interface controller from interconnection strategy selection, interface protocol establishment and memory timing parameters. sgram is one of the successful graphics device with high performance and high speed in the multimedia technology application area recently. fsm resolve the arbitration mechanism and timing matching problems in the sgram controller design

    在存儲器性能確定的情況下系統如何高效率地使用該存儲器決定於其介面控制電路設計的優劣。本文從介面策略選擇、介面協議制定以及存儲器遲滯參數入手討論如何設計性能優良的存儲器介面。 sgram是近年來出現的較為成功的面向多媒體技術的內存器件之一，是一種高性能、高速度圖像存儲器。
  5. The control strategy of engine has been studied. the cmac ( cerebellar model articulation controller ) is used on electronic controlled lpg fuelled engine ' s optimizing, it is involved that the air fuel ratio and ignition timing

    對發動機的控制策略進行研究，首次將小腦模型神經網路（ cmac ）用於電控lpg發動機的優化控制，研究分析其用於空燃比控制和點火提前角控制的基本方法。
  6. In can - bus communication technique, the circuit design method of can - bus node and the technique of structuring distributed can - bus controlling network are put forward, how to realize can calling and broadcasting communication under pelican mode is explained thoroughly, and the computational technique of bit - timing parameter of can controller sja1000 is detailed

    在can總線通信技術中，給出了can總線節點電路的設計方法和基於can總線的分散式控制網路的組建方法，詳細論述了增強模式下can總線分散式控制網路實現點名和廣播通信的原理與方法，深入探討了can控制器sja1000位定時參數的計算方法。
  7. The fourth chapter introduces the circuit design method of can - bus node, as well as the technique of structuring distributing - type can - bus measuring and controlling network, explains thoroughly how to realize can calling and broadcasting communication under pelican mode, and discusses detailedly the computational technique of bit - timing parameter of can controller sja1000. the latter part of this chapter points out several important problems confronted and solved by the author in the course of designing can - bus communication system

    第四章介紹了can總線節點電路的設計方法和基於can總線的分散式測控網路的組建方法，詳細論述了增強模式下can總線分散式測控網路實現點名和廣播通信的原理與方法，深入探討了can控制器sja1000位定時參數的計算方法，總結了作者在設計can總線通信系統的過程中遇到和解決的幾個關鍵問題。
  8. The problem of local parameter optimization in low synchronization bunch _ rank speed - control system has been researched in this paper. the paper analyzed the problems existing in trational double closed _ loop bunch _ rank speed - control system, and pointed out the influence on performance of system caused by nonlinear parameter with timing variety. added a local mit self _ adaptive controller to double _ closed loop bunch _ rank speed - control system. the results of computer imitating indicated that under same disturbance the performance of system has been improved obviously. 5figs., 1tab., 4refs

    對低同步串級調速系統中局部參數最優化問題進行了分析研究.從理論上分析了傳統的雙閉環串級調速系統中存在的問題，指出了系統中非線性時變參數對系統性能的影響.在雙閉環串級調速系統中增加局部mit自適應規則.計算機模擬結果表明:在相同的擾動作用下，系統的性能得到明顯改善.圖5 ，表1 ，參4
  9. This dissertation finishes the design of pci bus target controller, with vhdl description of register transfers level. and it has also completed the function simulation as well as timing simulation after placing & routing. a fpga on pcb board is designed to test the target controller and the result of test meets basal function demand

    本論文完成了pci總線目標設備控制器的設計，採用vhdl對其進行了rtl級的描述，並且通過編寫測試激勵程序完成了功能模擬，以及布局布線后的時序模擬，通過fpga在pcb實驗板上進行硬體模擬，證明所實現的pci目標設備控制器符合基本功能要求。
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