實用寄存器 的英文怎麼說

中文拼音 [shíyòngjìcúnqì]
實用寄存器 英文
utility register
  • 實 : Ⅰ形容詞1 （內部完全填滿 沒有空隙） solid 2 （真實; 實在） true; real; honest Ⅱ名詞1 （實際; 事實...
  • 用 : Ⅰ動詞1 （使用） use; employ; apply 2 （多用於否定: 需要） need 3 （敬辭: 吃; 喝） eat; drink Ⅱ名...
  • 存 : 動詞1 （存在; 生存） exist; live; survive 2 （儲存; 保存） store; keep 3 （蓄積; 聚集） accumulat...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  1. Using shift registers to realize full sequence generators

    用移位寄存器實現滿序列發生器
  2. The chip simulation network laboratory system this paper disguessed is a distribute network simulation system based on lan. the system ' s architecture is a c / s of three lays. the front platform are the chip simulation network system application program terminer ; the middle lay is a dcom server, it ' s duty is to deal with the communication and data transmission between the terminer and then database server, and to execute the logical operation. the application program just connect with the middle lay and get data from it, the connection and operation with database server will be managed by the dcom server. the duty of database server is to access and backup the final data

    具體是由位於網路各個終端的晶元模擬網路實驗系統應用程序為前臺；中間層為dcom應用程序服務器，負責處理前臺應用程序與后臺數據庫的通信和數據傳輸，並執行業務邏輯，前臺應用程序只需要與應用程序服務器建立連接，在中間層操作數據即可，與后臺數據庫的連接和操作由應用程序服務器來統一管理操作。后臺數據庫只負責數據的存取操作。本論文實施的晶元模擬網路實驗系統模擬了主要的邏輯電路器件， 8088cpu ，存儲器，寄存器，數據總線，地址總線和控制總線，及其它相關晶元。
  3. Meanwhile, the implementation of such block cipher as rijndael with shifting registers is designed with performance as good as that of he method of table - lookup

    將移位寄存器實現高效流密碼的思想用於分組密碼rijndael演算法的實現，獲得與查表法相當的效率。
  4. For the real time performance need of the low speed speech compress algorithm and the asic implement of the transfer process between programs, the design is put forward in the paper, in which state registers control the cross access between operator and memory, register windows are used for the parameters transfer, and the technique of hardware controlling is used to avoid pipeline conflict, so that the main problems of the transfer process in tr600 are solved effectively

    摘要針對低速率語音壓縮演算法對處理器系統實時處理復雜運算的性能要求，就程序調用過程的asic實現問題進行了對比與分析，進而提出了用層次狀態寄存器控制存取運算元對存儲體交叉訪問的方法，並結合運用寄存器窗口傳遞參數的功能，以及利用空指令硬布線處理流水線沖突的方法，有效地解決了tr600晶元中調用過程存在的主要問題。
  5. The goal of this thesis is to accomplish base - band channel coding / decoding, fh framing / de - framing and fh synchronization, and also to control the modulator and demodulator in the prototype system. all these functions are implemented with a tms320vc5409 dsp

    作為項目的一個重要組成部分，本文採用dsptms320vc5409實現了基帶處理部分的通道編解碼、跳頻意義的組拆幀和跳頻同步、並對調制解調晶元讀寫寄存器進行了配置。
  6. Focusing on a 64 - bit high - performance general purpose microprocessor with fully independent intellectual property, the thesis investigates a 128 - word 65 - bit general register file with 12 - read and 8 - write ports which is a representational one for its large - scale and multi - port characteristics in that microprocessor, and realizes its full custom design with high speed in read and write access. from the layout simulation result, under the 0. 18um process, the upper limit working frequency for the register file is 900mhz

    本文面向一款具有完全自主知識產權的64位高性能通用處理器，對其中具有代表性的128字65位12讀埠和8寫埠的通用寄存器文件進行研究，實現了它的高速讀寫全定製設計，版圖模擬結果表明，在0 . 18um工藝下，設計可以工作的時鐘頻率上限為900mhz 。
  7. Chapter five discusses the design and the process of the generation of the control function, including counter, accumulator, comparator, shift register, demultiplexer, collector, access record. chapter six gives some advice and opinions on how to improve this computer software

    其次介紹了計數器、累加器、比較器、多路輸出選擇、移位寄存器控制項；數據類中的收集器、訪問記錄/部分輸出記錄等控制項的功能介紹和編程思路以及使用實例第六章對平臺的完善和改進闡述了一些個人的建議和想法。
  8. And more than 70 % hardware are tested during microcode self - test since the execution of micro program can cover other data paths. boundary scan is designed according to ieee1149. 1, and some other instructions such as degug, runbist are provided to support internal fault testing, online debugging and built - in self - test besides the several necessary insructions. internal scan is implemented by partial scan, through this the boundary of logic component and user - cared system registers can be selected to be scanned

    Bist用於測試cpu的微碼rom ，其它ram則利用微碼rom中的微程序進行測試，而微程序的運行則可以順帶覆蓋其它數據通路，從而使高達70 %的硬體得到測試;邊界掃描按ieee1149 . 1標準設計，除必備的幾條邊界掃描指令外，還提供了debug 、 runbist等指令以支持內部故障測試、在線調試及內建自測試;內部掃描採用部分掃描策略，選擇邏輯部件的邊界及用戶關心的系統寄存器進行掃描，從而實現了硬體邏輯劃分，方便了后續的測試碼產生和故障模擬，並為在線調試打下了基礎。
  9. Moreover, regulating the signals from the sub - detectors of besiii is the key technique that could determinates whether trigger system discriminates the good events. this paper describes a pipelined digital programmable delay module, which is to be used in the global trigger, designed as a single width 6u standard vme module. two main method are used in the preliminary design : one utilizes shit register and multiplexers, which is simple and reliable

    在預研製過程中，使用了兩種可編程的延遲方法並對比了這兩種方法：一種是利用移位寄存器與多路選擇器串聯來實現可編程的延遲，此方法簡單、可靠性強；另一種則是利用雙口ram具有的獨立的讀和寫地址線，在設計中使讀、寫地址間距可調來實現可編程延遲。
  10. Within this scope, users can get almost any frequency clock by configuring the register, as the tune - process is nearly continual ( in fact there are many discrete frequency points ). the main circuit of the clock generator is a cppll ( charge pump pll ) designed in a method

    該時鐘發生器可以向系統提供頻率范圍是93 . 75k - 180mhz的時鐘信號，用戶可以通過配置寄存器的方法使時鐘發生器輸出自己需要的頻率，而且這一調頻過程幾乎是連續的（實際上是眾多離散點構成的線性近似） 。
  11. This text introduced the work patterns and register structure of 80386 processors in detail at first, latterly expounded especially the hardware interrupt handling of windows 98 with the course to the kernel of windows 98 ; then recommended the framework of realization of highly demanding hardware board interrupt handling by revising idt to intercept interrupt handling at hardware layer, subsequently introduced the application and development of vxd technology to achieve interrupt handling overall all situations under the windows 98 platform ; finally introduced the b / s pattern network application development part of this topic, specifically introduced the jsp technology system, elaborated the communication between network application part and the hardware interrupt handling routine combined with the jni technology, and provided partial important program and corresponding commentary

    本文首先詳細介紹了80386處理器的工作模式和寄存器結構，接著對windows98的內核進行了相關分析，重點介紹了windows98的硬體中斷處理過程;隨后介紹了通過修改中斷向量表以實現在硬體層截獲中斷來實現高實時性處理的框架，又介紹了windows98下虛擬設備驅動vxd技術的應用與開發，以及中斷全局處理的實現;最後介紹本課題的b / s模式網路應用開發部分，具體介紹了jsp技術體系，並結合jni技術闡述了網路應用與硬體中斷處理程序的通信，並給出部分關鍵程序及其注釋。
  12. H. 323 is the standard about multimedia communication released by itu - t. tm1300 including a very powerful, general - purpose vliw processor core ( the dspcpu ) that coordinates all on - chip activities is a media processor for high - performance multimedia applications that deal with high - quality video and audio. the dspcpu implements a 32 - bit linear address space and 128, fully general - purpose 32 - bit registers

    H . 323是itu ? t推出的用於ip分組網路的多媒體通信終端協議， trimediatm1300處理器晶元是philips公司推出的一種基於多媒體應用的具有vliw指令，含有128個通用寄存器， 32位的高性能處理器，它能夠通過編程實現通信協議，完成高質量的音頻、視頻處理和網路介面。
  13. In this paper, the methodology and implementation with hdl of design based reconfigurable architecture are discussed in detail, which includes the implementations of algorithms circuit, register file with controllable node, decoder, interface and main controller. from the introduction of design process of every module circuit, we can see easily some general feature of vlsi design with hdl

    在此基礎上詳細討論了基於可重組體系結構的密碼晶元設計方法和各電路實現的結構圖，包括演算法電路、可控節點寄存器堆、譯碼電路、介面電路和主控模塊電路等。通過對各個模塊設計過程的介紹，闡明了使用hdl語言設計超大規模集成電路的一般特點。
  14. If the chip remains sending state, it will take the data spread spectrum and modu - late, then sent forth by ad9768. the chip can be controlled throug h writing data in the interior 87 registers. secondly, this paper designed control system of twice civil air defense alarm system. because the scm " s port number was limited and port driving power is feebleness, this design realizes nixie tube ' s display drive with keyboard management chip max7219 and realizes true time display with ds1302, which can economize scm i / o port and make circuit connection simplicity

    通過對其內部87個寄存器寫入數據可對其進行控制。其次，本文對二次人防警報系統控制系統進行設計，針對單片機埠數目有限、埠驅動能力較弱等問題，使用鍵盤管理晶元max7219實現數碼管顯示驅動，用ds1302實現真時鐘顯示，節省了單片機i / o口，電路連接簡單。
  15. A raw ( read after write ) dependency loop model is developed in this paper to analyze the raw hazards of register operands in complex pipeline. based on this model, a " dynamic " data forwarding policy is suggested to reduce the pipeline stalls caused by data raw hazards. theoretical analysis and practical experiments both show that the average cpi increment caused by data raw hazards can be reduced effectively by the dynamic data forwarding strategy

    對于單發射結構的處理器，降低cpi值的根本途徑在於通過各種軟硬體技術減少流水線的停頓，本文構造了一個raw相關環路模型用於分析流水線中寄存器操作數的raw競爭現象，並提出了一種「動態」數據旁路優化策略，可以最大程度地減少復雜流水線中因數據的raw競爭而導致的互鎖停頓，理論分析和實測結果充分表明「動態」數據旁路機構可以有效地降低流水線因raw互鎖導致的平均cpi增量。
  16. A research is done for studying the reusable design principles of bus function model ( bfm ) and bus monitor for reusability. the functional verification framework is proposed in this dissertation can be apply in soc system level, rtl level and gate level verification. we accumulated experiences to soc functional verification

    討論了功能驗證平臺中總線功能模型（ busfunctionmodel ， bfm ）和總線監視器（ busmonitor ）的設計方法，給出了可重用設計的規則；本論文建立的soc功能驗證系統結構，可以應用於較大規模的soc的系統級、寄存器傳輸級和門級的驗證中，通過本課題研究，為國內soc功能驗證積累經驗，為國家超大集成電路的發展奠定一個堅實的基礎。
  17. Optimizing with profile data results in better register allocation. basic block optimization

    寄存器分配用配置文件數據進行優化，可以實現更好的寄存器分配。
  18. The powerpc architecture is organized into three instruction - set levels called " books. " book i is the base set of user instructions and registers that should be common to all powerpc implementations

    Powerpc體系結構的指令集分為三級，稱為「 books 」 。 book i是基本的寄存器和指令集，所有的powerpc實現都通用。
  19. The code length is very large when it be used. also, a significant amount of memory is needed to store their parity - check matrices. in this way, the encoding problem of ldpc codes may be an obstacle for their applications because they have high encoding complexity

    Ldpc碼在應用時選定的碼長很長而且編碼實現時所需的用於存儲的寄存器數量非常多，這樣，其編碼復雜度特別大，成為應用的一個障礙。
  20. For each register we create a queue and the index of queue item means a function of executing time. the item in the queue is either null or an instruction whose operand is kept in this register

    該演算法利用寄存器隊列分析指令間的數據相關，能夠分析出指令間的所有寄存器相關，其特點是：數據流驅動；演算法簡單、實現效率高；并行成分的表示直觀。
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