鎖存器 的英文怎麼說

中文拼音 [suǒcúnqì]
鎖存器 英文
d latch
  • 鎖 : Ⅰ名詞1 （安在開合處使人不能隨便打開的器具） lock 2 （姓氏） a surname Ⅱ動詞1 （上鎖） lock up 2 ...
  • 存 : 動詞1 （存在; 生存） exist; live; survive 2 （儲存; 保存） store; keep 3 （蓄積; 聚集） accumulat...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  1. The channel counter and decoder provide the channel select information to the data latch and transmit logic circuits.

    通道計數器和解碼器向數據鎖存和傳送邏輯電路提供通道選擇信息。
  2. In this paper, a safe, reliable, and intellectual control plan is provided aiming at the heat charge for dwelling district, which contains epigynous machine responsible for data processing and hypogynous mahcine responsible for unlocking the valve, by means of serial communication between them, combining homemade three - channel valve, to adminstrate the charge data and the valve efficiently. the main idea is based on the homemade three - channel valve. the vavle is locked at peacetime, while it is opened with the help of open tool and a water flow in the caliduct. as soon as the flow stops, the valve locks automatically. the open tool has data in its memory, and implement function by lcd and keyborad. so it can identify data and drive motor, to open the valve intellectually. the epigynous machine database manage system administrator the dweller information, standard heat charge and payment infomation etc, including store, configure, query, print etc, then store in the memory of open tool. as a result, the plan can do well in the experiment

    此閥平時是鎖閉的，只有用開啟器配以暖氣片中的水流才可打開，一旦水流斷開，則此閥會自會鎖閉。而開啟器則是根據其存儲器中的數據配以液晶顯示及小鍵盤，完成數據確認及電機驅動，自動對相應用戶的三通閥打開特定角度，完成開啟任務。上位機數據庫管理系統完成對用戶信息、熱費標準、繳費信息等原始數據的常規管理，包括存儲、設置、查詢、列印等，最後將處理后的數據傳到開啟器中存儲。
  3. Two other effects are transient phenomenon called single event upset ( seu ) and single event latchup ( sel ). in this paper, some means to harden the devices against these phenomena are used. guard banding around nmos and pmos transistors greatly reduces the susceptibility of cmos circuits to lachup

    在本文設計中，採用雙環保護結構，大大的降低了cmos集成電路對單粒子閂鎖效應的敏感性；對nmos管採用環型柵結構代替傳統的雙邊器件結構，消除了輻射感生邊緣寄生晶體管漏電效應；採用附加晶體管的冗餘鎖存結構，減輕了單粒子翻轉效應的影響。
  4. In addition, make out in detail the design on inner combination logic and time logic of fpga, including series - parallel conversion, data selector, counter, flip - latch, timer, encoder, etc. at one time, not only pursuit flow of the data gathering system is illuminated, but also make use of in reason and effectively inner ram resource of fpga and build it in ping - pong framework

    另外，詳細的介紹了fpga內部的組合邏輯和時序邏輯的設計方案，包括串並轉換、數據選擇器、計數器、鎖存器、定時器、譯碼器等。並闡述了數據採集系統的工作流程，而且合理有效地使用了fpga內部的ram資源，將其構建成乒乓式結構。
  5. Secondly, compared with some other kinds of comparator structure and based on the preamplifier - latch fast - compare theory, a novel topology of cmos preamplifier latch comparator circuit is presented. considering trade - off between kickback noise and power dissipation, reference resistance value is optimized. according to the encode demands of different stage resolution, clock - control encode circuit is designed

    其後，在具體的子adc設計中，對比各比較器類型的優缺點，並基於預放大鎖存快速比較理論，提出一種新型高速低功耗預放大鎖存比較器電路拓撲;根據adc系統所允許的參考電壓最大波動限制，在回饋噪聲對輸入參考電平的影響和功耗之間折衷，確定優化的參考電阻串阻值;根據不同級精度的編碼要求，設計出時鐘控制編碼電路。
  6. Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo

    本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。
  7. Provides a secure connection between the hard drive and the cable connector via a locking latch mechanism. ideal for

    -透過鎖定鎖存器裝置，為硬碟機和電纜連接器之間提供安全的連接。
  8. Based on the research and analysis of system structure of 10 - bit 100msps pipelined cmos adc, according to the system performance, the specifications of sub _ adc is obtained, while the sub _ adc including the preamplifier - latch comparator, the reference ladder resistance and the clock - control encode circuits are discussed in detail

    基於對10 - bit100mspspipelinedcmosadc系統結構的分析研究，結合系統性能確定了子adc的指標要求，詳細討論並設計了子adc單元模塊的設計，包括預放大鎖存比較器，參考電阻串和時鐘控制編碼電路。
  9. The four fold - frequency subdivision 、 direction - judgment 、 counting and flip - latch of the data which come from the six encorders are totally transacted in the fpga chip. the final data are sent to the pc through the serial interface of the fpga

    坐標測量儀的六個編碼器所傳出的數據完全在fpga晶元中進行細分、辨向、計數以及鎖存傳輸處理，最後所得的數據以串列通訊的方式傳送到pc機。
  10. Controlling system is composed of drive circuit, locking memory, shift register. temperature compensating circuit and drive power circuit are also needed

    控制系統是由驅動電路、鎖存器、移位寄存器等組成，此外還需要溫度補償電路和驅動電源電路，本文對控制系統進行了詳細的論述。
  11. The paper is completed research of measurement and control system based on dsp under technology. the paper is designed a card with the data - collection conversion and control by adopting mainly tms320f240 among the dsps as kernel processor, with peripheric a / d and d / a circuit epm7128 ' s decode and latch circuit and isa interface circuit

    本論文主要是採用數字信號處理器dsp中的tms320f240作為核心處理器，結合外部的模數轉換和數模轉換電路、可編程邏輯器件epm7128的地址譯碼和鎖存電路和isa介面電路，設計了集採集、轉換、控制於一身的isa卡。
  12. Once digitized at baseband, they can be stored in memory and recalled to generate the desired waveform

    設計中大量的使用了ecl邏輯的晶元，諸如鎖存器，移位寄存器等等。
  13. The host pc and terminal machine communicate with each other by udp, and the reading of ic card is through serial port. the measuring apparatus consists of analog switch, ad converter ads1256 circuits while the filtering apparatus is composed of latch 74hc374

    控制箱通過udp協議和pc通訊，通過串口讀寫ic卡;檢測儀主板主要由模擬開關和ads1256的電路組成;分選儀主板則主要是由74hc374鎖存器組成的分選電路。
  14. Circuit design is the basis of design of demultiplexer. speed, power and chip area are the main factors that should be considered in circuit design. every circuit structure has its merits and drawbacks, e. g. cmos logic family has a slower speed, but lower power, smaller area, scfl ( source couple fet logic ) family has a higher speed, but higher power, larger area. we should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors. flip - flop is the fundamental element of demultiplexer, setup time and hold up time are key factors, which influence the speed of circuit, thus the design aim is how to reduce them. in this thesis we place emphasis on the design of scfl latches

    速度、功耗、面積是電路設計要考慮的主要因素，不同的電路形式具有不同的優缺點，如cmos互補邏輯電路功耗低，面積小，速度相對較慢； scfl （源極耦合fet邏輯）電路速度高，功耗和面積較大。所以要針對具體設計需要選用適當的電路形式或其組合結構，以滿足設計要求。觸發器是分接器的基本組成單元，建立時間和保持時間是影響電路速度的關鍵，所以減小建立時間和保持時間是觸發器設計的主要目標，本文著重介紹了scfl鎖存器的設計和優化方法。
  15. The test register is a special latch that can hold values from comparisons performed in the alu

    測試寄存器是個特殊鎖存，可以保存alu中比較所得的值。
  16. The program counter is a latch with the extra ability to increment by 1 when told to do so, and also to reset to zero when told to do so

    程序計數器也是個鎖存，但還能夠在指示下遞增1 ，還能夠在指示下復位為0 。
  17. This section addresses the timing relationships between transitions of one or more input signals that are necessary to ensure device functionality and applies only to sequential - logic devices ( e. g., flip - flops, latches, and registers )

    本節為一個或更多輸入信號之間的時序關系提供尋址，這些輸入信號是使器件發揮作用的必須信號，並且只應用於順序邏輯器件（比如觸發器、鎖存寄存器和寄存器） 。
  18. It has been playing an important role in equipping all kinds of arms and services for campaigns, tactical exercises and emergent actions etc. based on the detailed analysis of the exchange ' s architecture and implementing, this thesis points out some disadvantages of the device, such as too many absolute components, not very high enough reliability and security, very large size and weight, operating and maintaining difficultly. considering low power requirement and man - machine interface optimizing design at the same time, the thesis come up with an integrated design scheme to the previous device based on " mcu + cpld / fpga architecture " : ( 1 ) signal frequency dividing, timing frequency producing, 20 customers " led states controlling are implemented in cpld ; ( 2 ) decoding, latching data and controlling signals are implemented in cpld by bus interface between mcu and cpld ; ( 3 ) chip selecting principles and mcu idle mode design are completed under the consideration of low power requirement ; ( 4 ) operation by chinese lcd menus is adopted in the man - machine interface

    本項目以該交換機為研究對象，在詳細分析原設備的系統結構和功能實現方式的基礎上，指出該機型在使用過程中存在技術相對陳舊、分立元件過多、可靠性和保密性不夠、體積大、重量大、維修困難等問題，同時結合系統的低功耗需求和優化人機介面設計，本文提出基於「單片機+ cpld fpga體系結構」的集成化設計方案：在cpld中實現信號音分頻和計時頻率生成電路、 20路用戶led狀態控制電路； cpld與單片機以總線介面方式實現譯碼、數據和控制信號鎖存功能的vhdl設計；基於低功耗設計的器件選型方案和單片機待機模式設計；人機介面的lcd菜單操作方式。
  19. A raw ( read after write ) dependency loop model is developed in this paper to analyze the raw hazards of register operands in complex pipeline. based on this model, a " dynamic " data forwarding policy is suggested to reduce the pipeline stalls caused by data raw hazards. theoretical analysis and practical experiments both show that the average cpi increment caused by data raw hazards can be reduced effectively by the dynamic data forwarding strategy

    對于單發射結構的處理器，降低cpi值的根本途徑在於通過各種軟硬體技術減少流水線的停頓，本文構造了一個raw相關環路模型用於分析流水線中寄存器操作數的raw競爭現象，並提出了一種「動態」數據旁路優化策略，可以最大程度地減少復雜流水線中因數據的raw競爭而導致的互鎖停頓，理論分析和實測結果充分表明「動態」數據旁路機構可以有效地降低流水線因raw互鎖導致的平均cpi增量。
  20. In this paper design of some circuit including in a / d circuit is also analyzed, such as front analog circuit, sample clock circuit and data flip - latch circuit

    同時對高速轉換器件及轉換電路中包括前端模擬電路、采樣時鐘、後端數據鎖存等輔助電路設計進行了分析。
分享友人
分享到 Line

分享到臉書