柵電容 的英文怎麼說

中文拼音 [zhàdiànróng]
柵電容 英文
bate capacitance
  • 柵 : 柵名詞（柵欄） railings; paling; palisade; bars
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 電容 : electric capacity; capacitance; capacity
  1. The main computer is programmed under windows, while the assistant computer is programmed under dos. the last, based on the idea of module - structure, the software of the testing system are designed, thus this software system is compatible and transplantable to design again. the experiment of measuring principle is taken : take the xy flat of lathe as the parallel - pole device and adjust the angle of sensor, the rotating - probe can test the felloe mould in scanning way

    藉助虛擬儀器的思想，對測控系統進行了設計：採用光柵尺、光電編碼器測量可動部件的運動量，解析度高、誤差小；採用細分驅動的步進電機裝置，控制性能好；系統實施環境溫度的檢測、補償，提高了檢測精度；基於兩級微機組建測控系統：主機為人機界面，採用windows編程，從機用dos編程，實時性好；軟體設計採用兼容性和移植性好的模塊式結構，便於二次開發。
  2. This article introduces briefly the process of design and characteristic of structure of db930 tube and discusses the main problems of technology and technique which was met during the manufacture and the measures having been adopted are emphatically. it discusses the solve measures in following six aspects : the filament current is too large, carbon deposits during the carbonizing of cathode, the capacitance between the first grid and the second grid is too large, transpiring happens inside the tube, the insulation resistance between the electrodes is too lower when the filament is on and the ability of bearing high voltage is too lower

    本文簡略地介紹了db930的設計過程及其結構特點，重點論述了在試制過程中遇到的主要工藝技術問題及解決問題的措施，圍繞解決燈絲電流大、陰極碳化時積碳、一柵和二柵之間的電容大、管內蒸散、熱態時極間絕緣低、耐高壓的能力差等六個方面的問題進行了論述。
  3. Capacitive grid current

    柵極電容電流
  4. In the dissertation, the effects of the air slide - film damping on the capacitive accelerometers having different slot structures which are completely or partly etched, and fabricated by the anodic bonding between silicon and glass and bulk silicon micromachining process are researched by changing the distance between the moving structure and substrate, the thickness of the structure, the width of the completely etched slot structure, the depth of the partly etched slot structure according to the two well known air slide - film damping models

    對于橫向運動的體微機械器件，其周圍空氣表現為滑膜阻尼。本文基於滑膜阻尼的兩個模型，通過改變振子與襯底的間距、振子的厚度、刻透的柵槽的寬度、沒有刻透的柵槽的深度等參數，研究了這些參數對硅?玻璃鍵合工藝製作的體硅微機械電容式傳感器阻尼特性的影響。
  5. Charge pump circuits that make use of charge accumulation in the capacitor can pump charge upward to produce voltage higher than the regular supply voltage, and they are widely used in memory circuits, such as flash memory, for the programming and erasing of the floating - gate devices

    電荷泵是一種運用電荷在電容中的積累來產生高壓（高於電源電壓）的電路，它廣泛應用在存儲器電路中，諸如flashmemory ，用於對懸浮柵器件進行寫或擦除操作。
  6. The new digital caliper improves the sensor system by designing a new structure of 3d shielding, which offers effective protection to the signal during transferring

    一途電子有限公司成立於1999年，致力於非接觸式容柵傳感器的開發和數顯量具機械結構的改進。
  7. Grid filament capacitance

    柵極燈絲電容
  8. It is shown that neglecting the gate - drain capacitance of the mosfet would lead to an overestimation of the optimum device width in the cmos source degenerated lna

    本文證明了在cmos源端degeneration結構的低噪聲放大器中，忽略場效應管的柵漏電容將造成對放大管的最優柵寬估計過大。
  9. It is believed that p - si tft will be the main type in the future panel display. among the process of manufacture p - si tft, the source and drain will have the superposition with grid for the reason of machine ’ s alignment error. the superposition will bring superposition capacitance and it will badly cut down the electric performance

    在制備多晶硅tft時，由於機器的套準誤差會在柵極與源、漏極之間產生重疊部分，這樣就造成了柵源、柵漏之間的交疊電容，交疊電容的存在嚴重影響了多晶硅tft的性能，而利用自對準工藝制備的多晶硅tft則避免了交疊電容的產生。
  10. Xing su ( microelectronics and solid state electronics ) directed by prof. lin chenlu the fast development of information technology requires integrated circuit to be greater integrated, faster functioned, and lower power - consumed, that lead to continuous shrinkage of mos and dram feature size. and under this trend the thickness of mos gate dielectrics ( sio2 ) would soon scale down to its physical limit

    日益增長的信息技術對更高集成度、高速、低功耗集成電路的需求，驅使晶體管的尺寸越來越小，隨之而來的問題是作為mos柵氧化物和dram電容介質的sio _ 2迅速減薄，直逼其物理極限。
  11. Abstract : a new approach, gate - capacitance - shift ( gcs ) approach, is described for compact modeling. this approach is piecewise for various physical effects and comprises the gate - bias - dependent nature of corrections in the nanoscale regime. additionally, an approximate - analytical solution to the quantum mechanical ( qm ) effects in polysilicon ( poly ) - gates is obtained based on the density gradient model. it is then combined with the gcs approach to develop a compact model for these effects. the model results tally well with numerical simulation. both the model results and simulation results indicate that the qm effects in poly - gates of nanoscale mosfets are non - negligible and have an opposite influence on the device characteristics as the poly - depletion ( pd ) effects do

    文摘:提出了一種新的建立集約模型的方法，即柵電容修正法.此方法考慮了新型效應對柵電壓的依賴關系，且可以對各種效應相對獨立地建模並分別嵌入模型中.另外，利用該方法和密度梯度模型建立了一個多晶區內量子效應的集約模型.該模型與數值模擬結果吻合.模型結果和模擬結果均表明，多晶區內的量子效應不可忽略，且它對器件特性的影響與多晶耗盡效應相反
  12. We can obtain the trap density by measuring the change of gate voltage of mos capacitance under constant current stress and the change of high frequency c - v curve before and after the stress

    該方法根據電荷陷落的動態平衡方程，測量恆流應力下mos電容的柵電壓變化曲線和應力前後的高頻cn曲線變化求解陷階密度。
  13. The core contents of digital power transmission network are to build the true three dimension scene of objective region, to search for the transmission equipments and to operate them in the scene interactively. according to the two main kinds of three dimension digital models ( earth surface model and transmission equipment model ), this thesis describes a simplifying method depended on view - point : it accomplishes displaying and flying over a large area of true earth surface with level of detail model based on block - binary tree. and it realizes " the efficient display of abundant data of equipment models and interactive management by the method of combination of models and images

    構建目標區域的真實三維場景，並在場景中對輸電設備進行查詢和交互操作是數字輸電網路的核心內容，本文針對數字平臺中兩種主要的三維數據模型? ?地表模型及輸電設備模型提出了基於視點的簡化方法：用塊? ?二叉樹結構的動態細節層次模型解決了大區域真實地形的顯示及漫遊方法；用失柵結合的方式實現了對海量設備模型數據的高效顯示及交互管理的功能。
  14. The model of threshold voltage solves the problems of nonuniformly doped channel, short channel effect, implantation for adjusting threshold voltage, edge capacitance of gate, etc. not only the model can be used in ldmos, but it can perfectly describe the short channel effect of threshold voltage for all other mos devices

    其中，閾值電壓模型解決了溝道非均勻摻雜、短溝道效應，調閾值注入，柵邊緣電容等問題。該模型不僅適用於ldmos ，也可以很好地描述所有的mos器件閾值電壓的短溝道效應，嚴格證明了短溝道效應會引起閾值電壓的減小。
  15. The chip is accomplished in the full cooperation with other team members, the author pays particular attention to the analysis of the whole chip architecture and three sub - block design : transconductance amplifier ( ota ), voltage reference and current reference. based on existed technologies, a new high order temperature compensated voltage reference and a creative current reference with high order temperature compensation are shown respectively. the author simulated all the sub - block and whole chip by hspice

    該晶元的設計是由小組成員共同完成，本人主要負責了總體電路的分析、聯合模擬驗證及以下三個子電路的設計: 1 、跨導放大器，詳細分析了bandgap跨導放大器輸入級的動靜態特性及其優缺點，並結合系統要求，設計了一種與cmos工藝相兼容、可替代bandgap跨導放大器的低壓共源共柵跨導放大器。
  16. The lna with source inductor degeneration is analyzed in detail, which is used most widely in current. base on the analysis, a cascode structure is presented to minimize the effect of gate - drain capacitance cgd

    針對目前lna中應用最廣泛的源極電感負反饋結構，進行了詳細分析，在此基礎上對該結構做出了優化，採用共源共柵級聯結構，減小了柵漏電容cgd的影響。
  17. Finally the method of preparation of p - si tft and some useful dates were given. the dissertation includes seven chapters. the first chapter introduces the development of tft ; the second chapter introduces the principle of tft and its structure ; the third chapter provides the reason of superposition capacitance between s, d and gate ; the fourth chapter introduce the deposition and test method of sinx ; the fifth chapter introduces the fabrication of p - si ; the sixth chapter studies the fabrication techniques of p - si tft and some parameters ; the seventh chapter is a conclusion of the research

    本文一共分為七章:第一章介紹了本論文的研究背景、研究意義、主要工作以及國內外的研究進展;第二章介紹了tft的結構和工作原理;第三章介紹了柵極與源、漏極之間疊加電容產生的原因和自對準工藝;第四章介紹了氮化硅的制備方法和測試方法;第五章介紹了多晶硅tft有源層的制備方法並對各種晶化機理做了介紹;第六章主要對利用自對準工藝制備tft的工藝進行研究，並對制備出來的樣品進行了測試;第七章對全文進行總結。
  18. Grid input capacitance

    柵極輸入電容
  19. Lead acid batteries - stationary vented batteries with positive grid plates - rated capacities, main dimensions, weights

    鉛酸蓄電池.帶正柵極板的固定式通風蓄電池.額定電容
  20. During the course of modeling ldmos, the paper puts forward the method in which maxwell function in the static system is applied in analysis compute of ldmos threshold voltage. schwarz - chritoffel transformation method is used to solve the gate self - capacitance with limited size. at the same time, it also provides the method which computes the drain and source self - capacitance by conformal transformation and the equivalent - voltage sharing - charge model

    在對ldmos的建模過程中，本文提出了將靜電系統中麥克斯韋方程用於ldmos閾值電壓的分析計算的方法，引入了許瓦茲-克利斯多菲變換來求解了有限尺寸的柵自電容，並提出了用保角變換和等電壓電荷共享模型來計算漏與源的自電容的方法。
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