現行寄存器 的英文怎麼說

中文拼音 [xiànhángjìcúnqì]
現行寄存器 英文
actual register
  • 現 : Ⅰ名詞1 （現在; 此刻） present; now; current; existing 2 （現款） cash; ready money Ⅱ副詞（臨時; ...
  • 行 : 行Ⅰ名詞1 （行列） line; row 2 （排行） seniority among brothers and sisters:你行幾? 我行三。where...
  • 存 : 動詞1 （存在; 生存） exist; live; survive 2 （儲存; 保存） store; keep 3 （蓄積; 聚集） accumulat...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 現行 : 1. （現在施行的; 現在有效的） currently in effect; in force; in operation 2. （正在進行犯罪活動的） active
  1. The information of running programs users can get is just the register, memory and symbol state

    所看到的程序執行現狀，也只是目標機方當前程序寄存器、內存、符號信息等基本信息。
  2. For the real time performance need of the low speed speech compress algorithm and the asic implement of the transfer process between programs, the design is put forward in the paper, in which state registers control the cross access between operator and memory, register windows are used for the parameters transfer, and the technique of hardware controlling is used to avoid pipeline conflict, so that the main problems of the transfer process in tr600 are solved effectively

    摘要針對低速率語音壓縮演算法對處理器系統實時處理復雜運算的性能要求，就程序調用過程的asic實現問題進行了對比與分析，進而提出了用層次狀態寄存器控制存取運算元對存儲體交叉訪問的方法，並結合運用寄存器窗口傳遞參數的功能，以及利用空指令硬布線處理流水線沖突的方法，有效地解決了tr600晶元中調用過程存在的主要問題。
  3. The goal of this thesis is to accomplish base - band channel coding / decoding, fh framing / de - framing and fh synchronization, and also to control the modulator and demodulator in the prototype system. all these functions are implemented with a tms320vc5409 dsp

    作為項目的一個重要組成部分，本文採用dsptms320vc5409實現了基帶處理部分的通道編解碼、跳頻意義的組拆幀和跳頻同步、並對調制解調晶元讀寫寄存器進行了配置。
  4. Focusing on a 64 - bit high - performance general purpose microprocessor with fully independent intellectual property, the thesis investigates a 128 - word 65 - bit general register file with 12 - read and 8 - write ports which is a representational one for its large - scale and multi - port characteristics in that microprocessor, and realizes its full custom design with high speed in read and write access. from the layout simulation result, under the 0. 18um process, the upper limit working frequency for the register file is 900mhz

    本文面向一款具有完全自主知識產權的64位高性能通用處理器，對其中具有代表性的128字65位12讀埠和8寫埠的通用寄存器文件進行研究，實現了它的高速讀寫全定製設計，版圖模擬結果表明，在0 . 18um工藝下，設計可以工作的時鐘頻率上限為900mhz 。
  5. A design method based on multiplexing execution - cycle and interrupt flag signals using register model is proposed

    提出了中斷執行周州復川、寄存器模型設計中斷標識信號的中斷電路實現方法。
  6. And more than 70 % hardware are tested during microcode self - test since the execution of micro program can cover other data paths. boundary scan is designed according to ieee1149. 1, and some other instructions such as degug, runbist are provided to support internal fault testing, online debugging and built - in self - test besides the several necessary insructions. internal scan is implemented by partial scan, through this the boundary of logic component and user - cared system registers can be selected to be scanned

    Bist用於測試cpu的微碼rom ，其它ram則利用微碼rom中的微程序進行測試，而微程序的運行則可以順帶覆蓋其它數據通路，從而使高達70 %的硬體得到測試;邊界掃描按ieee1149 . 1標準設計，除必備的幾條邊界掃描指令外，還提供了debug 、 runbist等指令以支持內部故障測試、在線調試及內建自測試;內部掃描採用部分掃描策略，選擇邏輯部件的邊界及用戶關心的系統寄存器進行掃描，從而實現了硬體邏輯劃分，方便了后續的測試碼產生和故障模擬，並為在線調試打下了基礎。
  7. This text introduced the work patterns and register structure of 80386 processors in detail at first, latterly expounded especially the hardware interrupt handling of windows 98 with the course to the kernel of windows 98 ; then recommended the framework of realization of highly demanding hardware board interrupt handling by revising idt to intercept interrupt handling at hardware layer, subsequently introduced the application and development of vxd technology to achieve interrupt handling overall all situations under the windows 98 platform ; finally introduced the b / s pattern network application development part of this topic, specifically introduced the jsp technology system, elaborated the communication between network application part and the hardware interrupt handling routine combined with the jni technology, and provided partial important program and corresponding commentary

    本文首先詳細介紹了80386處理器的工作模式和寄存器結構，接著對windows98的內核進行了相關分析，重點介紹了windows98的硬體中斷處理過程;隨后介紹了通過修改中斷向量表以實現在硬體層截獲中斷來實現高實時性處理的框架，又介紹了windows98下虛擬設備驅動vxd技術的應用與開發，以及中斷全局處理的實現;最後介紹本課題的b / s模式網路應用開發部分，具體介紹了jsp技術體系，並結合jni技術闡述了網路應用與硬體中斷處理程序的通信，並給出部分關鍵程序及其注釋。
  8. If the chip remains sending state, it will take the data spread spectrum and modu - late, then sent forth by ad9768. the chip can be controlled throug h writing data in the interior 87 registers. secondly, this paper designed control system of twice civil air defense alarm system. because the scm " s port number was limited and port driving power is feebleness, this design realizes nixie tube ' s display drive with keyboard management chip max7219 and realizes true time display with ds1302, which can economize scm i / o port and make circuit connection simplicity

    通過對其內部87個寄存器寫入數據可對其進行控制。其次，本文對二次人防警報系統控制系統進行設計，針對單片機埠數目有限、埠驅動能力較弱等問題，使用鍵盤管理晶元max7219實現數碼管顯示驅動，用ds1302實現真時鐘顯示，節省了單片機i / o口，電路連接簡單。
  9. After deeply studying all kinds of problems of current actualization methods, we put forward to a new actualization method of the technology of physical isolation on the base of cpld. we make a lot of research on data encryption and describe the design method of the encryption chip on the base of lfsr ( linear feedback shift register ). after putting forward to the whole design procedure, we design an encryption chip on the base of lfsr, which can provide the high - quantity data stream of encrtption

    在深入研究了常見物理隔離技術實現方案中存在的各種問題后，提出了一種基於cpld的全新實現方案；同時，對于存儲信息的加密也進行了研究，詳細闡述了基於移位寄存器的非線性組合序列密碼的設計方法，提出了完整的設計流程，並設計了一個基於fpga的非線性組合反饋序列密碼晶元，該晶元能提供高質量的偽隨機密鑰流。
  10. If an application switches out of kernel mode and one of its upper 96 registers is not intact, as could happen if an interrupt occurred, the application will fail when it switches back to user mode

    如果某個應用程序切換出內核模式，並且該應用程序上面的96個寄存器之一已發生變化（發生中斷時會出現這種情況） ，則該應用程序在切換回用戶模式后將無法運行。
  11. Optimizing with profile data results in better register allocation. basic block optimization

    寄存器分配用配置文件數據進行優化，可以實現更好的寄存器分配。
  12. A switch ic for analog signal processing is designed and implemented, which can fulfill the functions of sampling, weighting, controlling and summing of high frequency analog signals. the circuit consists of three parts : four channel analog switches, a voltage reference and the control circuitry. each analog switch is comprised of two high - transconductance n - mosfets with high w / l ratio, which realize the fine tuning and coarse tuning of the input signal respectively

    本文研究並設計了一種可對高頻信號進行取樣、加權、控制、疊加的模擬信號處理丌關集成電路，它包括模擬開關、電壓基準源和移位寄存器三個功能模塊，通過兩個高寬長比的高跨導nmos晶體管實現權值的粗調和微調。
  13. The serial a / d transformation and the channel isolation technology are adopted. eight - channel parallel data acquisition and test data time - sharing storage are realized. verilog hdl ( hardware description language ) is adopted to design the vxi register - based interface circuit and control circuit of each channel

    以fpga （ fieldprogrammablegatearray ）為控制核心，採用串列a / d變換器和通道隔離技術，實現了8通道并行採集和測試數據分時存儲功能，利用veriloghdl （ hardwaredescriptionlanguage ）設計vxi寄存器基介面電路及各通道的控制電路。
  14. Otherwise, as a memory component, large - scale register file holds a large number of data, so it requires stronger stability and validity. for memory components, using bist method to make a fault checking is a relatively good choice. but the bist of the multi - port register file is still in early phase of development

    另外作為存儲部件，規模大的寄存器文件現場保存量大，需要有很強的穩定性和正確性，而內建自測試是存儲部件進行故障檢測的較佳選擇;但是多埠寄存器文件的測試卻處在初始發展階段，故障模型和測試演算法都有待于進一步完善。
  15. For each register we create a queue and the index of queue item means a function of executing time. the item in the queue is either null or an instruction whose operand is kept in this register

    該演算法利用寄存器隊列分析指令間的數據相關，能夠分析出指令間的所有寄存器相關，其特點是：數據流驅動；演算法簡單、實現效率高；并行成分的表示直觀。
  16. Chapter 3 focuses on translating the c code into assembly code. the implementation and optimization involves issues of assignment of variables and memories, pass of function parameters, addressing modes, control of nested repetition, use of ar registers, pipeline conflicts, and so on

    本文從改寫c源碼為c54x匯編代碼著手，對實現過程中的變量存儲區分配、參數的傳遞、尋址方式的選擇、循環的嵌套與控制、輔助寄存器的使用、流水線等方面的問題進行了設計和優化，在c54x上實時實現了g . 729a聲碼器。
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