相對時鐘 的英文怎麼說

中文拼音 [xiāngduìshízhōng]
相對時鐘 英文
relative time clock
  • 相 : 相Ⅰ名詞1 （相貌; 外貌） looks; appearance 2 （坐、立等的姿態） bearing; posture 3 [物理學] （相位...
  • 對 : Ⅰ動詞1 （回答） answer; reply 2 （對待; 對付） treat; cope with; counter 3 （朝; 向; 面對） be tr...
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 相對 : 1. （面對面） opposite; face to face 2. （非絕對的） relative 3. （比較的） relatively; comparatively
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  1. Philadelphia, april 16 - michael jordan, 40 years of age and favoring crafty head fakes and jump shots rather than the acrobatic dunks and astounding hang time that made him famous, ended his storied playing career tonight

    費城， 4月16日已屆不惑之年的邁克爾喬丹，相對于令他四海揚名的雜耍般的扣籃，而後不可思議地長時間吊在半空的一系列絕活，更為鐘愛自己巧妙的頭部假動作和靈活的跳投。
  2. Additionally, protein bands were found in the range of 62 kd in microsomes from oryza sativa and 45 kd from arabidopsis thaliana -, 2 ) the ipar - like protein was mainly localized in the vacuolar membrane ( tonoplast ) and plasma membrane in the leaf and root tip of arabidopsis thaliana for confirming the biological role of the ip3r - like protein, we investigated the effects of methyl viologen ( stimulating ip3 produce ) and heparin ( a competitive inhibitor of inositol 1, 4, 5 - triphophate in animal ) on stomatal movement by epidermal strip bioassay. when the epidermal strips of arabidopsis thaliana were treated with methyl viologen, it stimulates the stomatal closure

    擬南芥表皮條用甲基紫精處理，可以引起氣孔的關閉，當處理90分鐘的時候，氣孔的相對開度由100降到58 ，統計學分析氣孔開度的變化有顯著差異；甲基紫精引起氣孔關閉的作用可以被肝素部分抑制，當甲基紫精和肝素同時處理90分鐘的時候，氣孔的相對開度由100降到92 ，統計學分析氣孔開度的變化沒有顯著差異，說明氣孔的相對開度基本上沒有變化。
  3. The three - order modulator has a 2 - 1 cascaded structure and 1 - bit quantizer at the end of each stage, the modulator is implemented with fully differential switched - capacitor circuits. and then, the discussion will begin by exploring the design of various circuit blocks in the modulator in more detail, i. e., ota, switched - capacitor integrator, quantizer, two - phase non - overlapping clock signal, etc., at the same time, these circuits will be simulated in spectre and hspice. at last, the whole cascaded modulator will do behavioral level simulation by matlab soft and simulink toolbox

    本論文中，首先介紹模數轉換器的各種參數的意義，以及一階sigma - delta調制器和高階sigma - delta調制器的原理;給出解決高階單環sigma - delta調制器不穩定性的方案，引入級聯結構調制器，特別針對級聯結構調制器中的失配和開關電容積分器的非理想特性進行詳細的討論;本設計的sigma - delta調制器採用2 - 1級聯結構和一位量化器，調制器採用全差分開關電容電路實現;同時對整個調制器的各個模塊進行了電路設計，包括跨導放大器、開關電容積分器、量化器、兩相非交疊時鐘等，並利用hspice和spectre模擬工具對這些電路進行模擬測試;最後，利用matlab軟體和simulink工具對整個級聯調制器進行行為級模擬。
  4. Reveals the objective necessity of the sole existence of absolute reference system 0 : the effect of clock losing and ruler contracting of any material system in motion with respect to 0 is the objective real physical change ( the real effect ) of this material system in motion, and the physical time and space ( the effect of motion ) is the unity of opposites between the external form of relativity correctly described by the special theory of relativity and the absolute internal essence with the objective sole existence of 0 as the basic marking, points out the errors of the general theory of relativity from the results above and the basic facts of gravitational field, and expounds the gravitational field is a real - time hollow field of motion in essence, and the physical time and space is the unity of opposites between mutually perpendicular images of void and real time and space of 4 dimensions each, understanding the absolute essence of the lorenz effect or not is the demarcation line between new and old views of time and space, and sets forth the theoretical gist of the time and space views of unity of opposites and the internal unity among the macroscopic level and straight time and space, the bent time and space in gravitational field, and the superimposed time and space in guantum state

    揭示了絕對參照系0唯一存在的客觀必然性：任何物系相對於0的「運動鐘慢、尺縮效應」 ，都是該運動物系客觀上具有蹬真正的物理變化（ 「真實效應」 ） ；進而揭示了物理時空（運動效應）是具有狹義相對論所正確描述了的相對性外部形式和以0客觀上唯一存在為基本標志的絕對性內在本質的對立統一運用上述結果和引力場的基本事實，論證了廣義相對論的錯誤；闡明了引力場本質上是一種實時虛空運動場；揭示了物理時空是互為正交映象的虛實各四維時空的對立統一闡明了對洛侖茲效應絕對性本質的認識與否，是新舊時空觀的分水嶺；闡明了對立統一時空觀的理論梗要和宏觀平直時空、引力場彎曲時空與量子態卷迭時空之間的內在統一性
  5. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  6. Object provides properties for accessing the current local time and universal coordinated time equivalent to greenwich mean time from the system clock

    My . computer . clock對象提供了一些屬性，可用於從系統時鐘訪問本地當前時間及協調通用時間（相當于格林威治標準時間） 。
  7. Gets an object that provides properties for accessing the current local time and universal coordinated time the equivalent to greenwich mean time from the system clock

    獲取一個對象，該對象可提供用於從系統時鐘訪問當前的本地時間和協調通用時間（與格林尼治標準時間相同）的屬性。
  8. In this paper, the design of a specific chip for circuit emulation based on ip is put forward and realized and the main functional modules and the key algorithms including an all - digital adaptive clock recovery method and a dynamic depth buffer algorithm are described in detail

    文章根據相關標準提出並實現了一種電路模擬專用晶元的設計方案，並對其中主要功能模塊和關鍵演算法作出了詳細說明，包括一種全數字的自適應時鐘恢復方法、動態深度緩沖演算法等。
  9. The clock recovery block of usb2. 0 transceiver macrocell consists of phase locked circuit, such as pll and dll ( delay locked loop ). this block use external crystal 12mhz sin signal to produce 60mhz, 120mhz, 480mhz clock signal, and can recover colock signal form date wave. it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2. 0 specification.

    目的是用鎖相環電路? pll和dll （延遲鎖相環）實現usb2 . 0收發器宏單元utm的時鐘恢復模塊。其中pll環路構成的時鐘發生器將外部晶振的12mhz正弦信號生成60mhz 、 120mhz 、 480mhz等本地時鐘信號。 dll環路依據本地時鐘信號對外部數據信號進行時鐘恢復。
  10. Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo

    本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。
  11. Chapter 3 treats the algorithm implementation of demodulator in the receiving asic of dvb - s. in detail, demodulation includes carrier recovery and symbol synchronization. together with the transmission characterization of band - limited input signals the chapter proposes a scheme for implementing carrier recovery loop

    解調具體分為載波恢復、時鐘同步兩大部分，本章著重論述了載波恢復的原理並結合dvb - s輸入信號傳輸特性，提出了相應的實現方案，對部分電路進行了性能分析。
  12. As concerning to the interference condition between different transmit / receive channels in the system, a detailed error analysis is given, and the clock and synchronization scheme is explicated. the measure adopted to enhance phase clock ' s precision is explained

    本文對超聲相控陣系統中各通道發射/接收的相干條件進行了詳細的誤差分析，闡明了本系統採用的時鐘和同步方案，以及改進相控陣時鐘精度的方法。
  13. And if the relative velocity of two inertial frames is constant, the compound pendulum in motion runs slower at a same factor than the resting one

    兩慣性系相對速度一定時，運動的復擺鐘都比靜止的鐘慢了一個相同的因子。
  14. A drive method of unequalized clock counter in panel display which uses no dissimilarity @ subclass to achieve precision unequalized clock counter correction based on functions approximation theory is proposed. the new method is acquired based on the particular analysis results of the display drive design projects which adopted counter drive method in which the balance between the display image quality and the cost of drive circuit is given. finally, synthesis comparison examples are given

    針對目前以該方法為基礎普遍採用的不同技術方案進行詳盡的分析，根據分析的結果闡明了其在圖像顯示質量和驅動代價方面的優缺點，在此基礎上基於函數逼近理論提出了一種平板顯示器計數器非均勻時鐘驅動方法，該方法在計數器時鐘上採用非相異子集完成高精度的非均勻時鐘計數器校正。
  15. The clocks in relative motion keep different times.

    處在相對運動狀態下的幾個鐘，所記錄下來的時間不同。
  16. The paper first reviews the research background and actuality of the filter " s design in china and other country, introduces the meaning of the project and the work of the paper, narrates the theory of the switched - capacitor network and the basic switch building blocks, analyses the related factors of the design of sc filter. such as the selection of the architecture, the trade off of the opamp " s gain, bandwidth, phase margin, slew rate and setting time, the effect of the switch " s on resistor, how to reduce the charge injection and the clock feed - through, the power consumption and the selection of the sampling frequency and so on

    本文首先回顧了濾波器設計的國內外研究背景和現狀，介紹了本課題提出的意義以及本文的主要工作，論述了開關電容網路原理和基本開關模塊，分析了開關電容濾波器設計的相關因素：電路結構的選擇，對運算放大器設計中高增益、寬帶寬、相位裕度、轉換斜率和建立時間等的折中考慮，開關的打開電阻對電路的影響，開關電容電路中怎樣減少電荷注入和時鐘饋通，以及整個電路的功耗問題和采樣頻率的選擇等。
  17. The means of transportation that i chose at ordinary times is the rail transportation basically, the subway or the light railway, because and fast, so long as than estimate more about one minute such as time, would not be late, and though its crowded degree is a bit serious, as to traffic above - ground, ones that can be accepted, will not seem too hot or too cold in hot summer and cold winter

    我平時選擇的交通工具基本上是軌道交通，地鐵或輕軌，因為相對而言比較準時而且快速，只要比預計時間多出15分鐘左右，就不會遲到了，而且其擁擠程度雖然有些嚴重，但相對地面交通來說，還是可以接受的，在炎熱的夏季和寒冷的冬季，都不會顯得太熱或太冷。
  18. Bits supplies the synchronous timing signal to these equipments inside the telecommunicationt building, such as dps, atm, no. 7, dxc, tm & adm in sdh, don and in etc. the related techniques are involved in the content of synchronization ne twork, timing distribution, the timing signal transportations x impairments etc. the second chapter tells the structure and the function of the building integrated timing system. the third chapter summarizes the digital synchronization network techniques, which emphasizes the basic concept of synchronization networks analyzes the necessity of building the synchronization network and introduces all kinds of synchronization methods. the fourth chapter represents the transportation of the synchronization signal

    本文第二章講述了通信樓綜合定時系統的構成及作用：第三章概述了數字同步網技術，著重描述了同步網的基本概念，分析了建立同步網的必要性，講述了各種同步方法；第四章闡述了同步定時信號的傳輸；第五章介紹了bits設備所支持的同步狀態消息；第六章、第七章為本文的重點，通過對時鐘信號建立數學模型，從理論上分析時鐘內部噪聲和相位瞬變產生時鐘定時信號損傷的原理，企圖尋找到更好地控制頻率漂移的方法。
  19. Statistical model for the spatial variability of soil properties

    分散式實時系統的集中式相對時鐘同步方法
  20. But to design and integrate a clock generator into a chip is a far cry from the out - chip one

    文中研究的鎖相環時鐘發生器就針對該要求而設計。
分享友人
分享到 Line

分享到臉書