譯碼集 的英文怎麼說

中文拼音 [yìmǎjí]
譯碼集 英文
decoding set
  • 譯 : 動詞（翻譯） translate; interpret
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 集 : gatherassemblecollect
  1. Bcd detail specification for electronic component. semiconductor integrated circuit. type ch2019 4 - line to 10 - line decoder with bcd - in

    電子元器件詳細規范.半導體集成電路ch2019型4線- 10線譯碼器
  2. In addition, make out in detail the design on inner combination logic and time logic of fpga, including series - parallel conversion, data selector, counter, flip - latch, timer, encoder, etc. at one time, not only pursuit flow of the data gathering system is illuminated, but also make use of in reason and effectively inner ram resource of fpga and build it in ping - pong framework

    另外，詳細的介紹了fpga內部的組合邏輯和時序邏輯的設計方案，包括串並轉換、數據選擇器、計數器、鎖存器、定時器、譯碼器等。並闡述了數據採集系統的工作流程，而且合理有效地使用了fpga內部的ram資源，將其構建成乒乓式結構。
  3. Based on the ( 3, 1, 5 ) convolution code in digital trunking system, this paper first studied the decoding depth of the convolution code and fund out the right decoding depth for digital trunking system, then proposed a modified viterbi decoding algorithm

    本文以數字集群中所用的（ 3 ， 1 ， 5 ）卷積碼為基礎，首先對卷積碼的解碼深度進行了研究，得出適合數字集群系統的解碼深度，然後提出了一種卷積碼的viterbi譯碼的改進演算法。
  4. The designing process of the edac circuit is described in the paper. the time simulation is analysed, too. the designment of the circuit has access the hardware debug, and can woks normally

    此外還將第一輪設計中的基本邏輯器件如與、或、非門以及諸如244 、 255 、譯碼器等小規模元器件都集成到fpga內部來實現。
  5. In this paper, we study the stopping sets, stopping distance and stopping redundancy for binary linear codes. stopping redundancy is a new concept proposed by schwartz and vardy recently for evaluating the performance of a linear code under iterative decoding over a binary erasure channel. since the exact value of stopping redundancy is difficult to obtain in general, good lower and upper bounds are important

    近年來，迭代譯碼的性能分析是低密度校驗ldpc碼研究領域的熱點問題之一， di等人在2001年指出：迭代譯碼在二元刪除通道bec中的性能可以由ldpc碼的停止集stopping set完全刻畫。
  6. Making logical designs with the integrated decoder

    用集成譯碼器進行邏輯設計
  7. Many of communication systems take the convolutional code and viterbi algorithm as the channel coding scheme. the viterbi algorithm decoding is a kind of maximum likelihood decoding, and its performance is good over additive white gaussian noise ( awgn ) channel, but when burst errors occur, the decoding performance may be greatly degraded

    維特比譯碼演算法是最大似然譯碼，在由高斯白噪聲引起的隨機錯誤的通道中有良好的性能，但當通道錯誤集中或為突發錯誤通道時，維特比譯碼演算法則性能急劇下降。
  8. This system presents us various kinds of user interfaces ( such as thin - client ui ), further more, to facilitate further research and provide a scientific foundation to ensure flight safety and daily monitor, other extended interfaces ( including network interface, data analysis interface, decode interface and etc ), are also provided by the system

    該系統由數據採集、譯碼、實時數據處理、實時監控模擬再現等模塊組成，系統還提供用戶介面、網路介面，數據分析介面，譯碼擴展介面等。該系統可以應用於航空公司機務維修等部門，結合地空數據鏈系統，為保障飛機飛行安全以及日常監控提供科學的依據，同時也為飛機油耗優化、技術評估等提供數據支持。
  9. In this paper we discuss mca circuit, the sequential logic for mca data collection, for the setting of the uld, lld and the gain of pga, as well as the combinational logic for decoding circuits of the computer interface, based on cpld

    本文詳細論述了利用cpld實現的脈沖幅度多道電路及其數據採集的時序控制邏輯、閾值設定和程式控制放大倍數設定的時序控制邏四川大學碩士學位論文輯、以及與計算機介面的譯碼電路等組合控制邏輯。
  10. Although the structure of stbc decoding is very simple, it can achieve the same diversity gain as the method of mrc, and its use of the spectrum is very high. because of these advantages, sttb is referred into the 3gpp1

    由於空時分組碼編譯碼器的結構相當簡單，卻能獲得與最大比合併相同的分集增益，並且它的頻譜利用率高，已經被引用到3gpp1中。
  11. Dna sequence can be seen as a character string including a, g, c and t which are like binary code " 0 " and " 1 " in computer science. hence, strands of dna are just sequences over the alphabet

    Dna鏈可看作由四個不同符號、 、和組成的串，它在數學上就像計算機中的編碼「 0 」和「 1 」一樣，可表示成四個字母的集合來譯碼信息。
  12. The whole paper had been divided into four parts : the first part introduces the general situation of digital trunking system and its channel encoding, the recent development of viterbi decoding ; the second part studies the error control scheme, and the convolution decoding depth which is most fit to digital trunking system ; the third part introduces several low power viterbi decoder and its principle ; the last part proposes a united - decision estimating viterbi decoding algorithm

    本文共分為四部分，第一部分介紹了數字集群及其通道編碼的總體情況， viterbi譯碼的發展現狀。第二部分給出了數字集群系統中話音通道差錯控制總體方案，並研究了適合數字集群系統的卷積碼的解碼深度。第三部分簡單介紹了各種低功率viterbi譯碼器及原理。
  13. The paper is completed research of measurement and control system based on dsp under technology. the paper is designed a card with the data - collection conversion and control by adopting mainly tms320f240 among the dsps as kernel processor, with peripheric a / d and d / a circuit epm7128 ' s decode and latch circuit and isa interface circuit

    本論文主要是採用數字信號處理器dsp中的tms320f240作為核心處理器，結合外部的模數轉換和數模轉換電路、可編程邏輯器件epm7128的地址譯碼和鎖存電路和isa介面電路，設計了集採集、轉換、控制於一身的isa卡。
  14. In detail, they are bit - interleaved coded modulation ( with iterative decoding ), low - density parity - check codes and stf technology. by the performance analysis of bicm ( - id ), which can make code and modulation optimal separately, and achieve maximum possible coding diversity as well as modulation gain, guidelines for its design and an easy algorithm for siso are proposed. design of capacity - approaching of ldpc codes and efficient encoding of them as well as several kinds of its decoding algorithms are investigated

    具體的講，就是討論了基於比特交織的編碼調制技術，並給出了映射方式的設計準則以及核心模塊siso的一種簡單的f - map演算法；研究了編碼最小漢明距隨碼長線性增加的ldpc碼的幾個方面的問題，包括接近香農限碼子集的度分佈對的設計、有效編碼器的實現和各種譯碼演算法的優缺點，並對基於ldpc碼的bicm應用於ofdm傳輸系統中的性能進行了模擬。
  15. It has been playing an important role in equipping all kinds of arms and services for campaigns, tactical exercises and emergent actions etc. based on the detailed analysis of the exchange ' s architecture and implementing, this thesis points out some disadvantages of the device, such as too many absolute components, not very high enough reliability and security, very large size and weight, operating and maintaining difficultly. considering low power requirement and man - machine interface optimizing design at the same time, the thesis come up with an integrated design scheme to the previous device based on " mcu + cpld / fpga architecture " : ( 1 ) signal frequency dividing, timing frequency producing, 20 customers " led states controlling are implemented in cpld ; ( 2 ) decoding, latching data and controlling signals are implemented in cpld by bus interface between mcu and cpld ; ( 3 ) chip selecting principles and mcu idle mode design are completed under the consideration of low power requirement ; ( 4 ) operation by chinese lcd menus is adopted in the man - machine interface

    本項目以該交換機為研究對象，在詳細分析原設備的系統結構和功能實現方式的基礎上，指出該機型在使用過程中存在技術相對陳舊、分立元件過多、可靠性和保密性不夠、體積大、重量大、維修困難等問題，同時結合系統的低功耗需求和優化人機介面設計，本文提出基於「單片機+ cpld fpga體系結構」的集成化設計方案：在cpld中實現信號音分頻和計時頻率生成電路、 20路用戶led狀態控制電路； cpld與單片機以總線介面方式實現譯碼、數據和控制信號鎖存功能的vhdl設計；基於低功耗設計的器件選型方案和單片機待機模式設計；人機介面的lcd菜單操作方式。
  16. In this paper, the methodology and implementation with hdl of design based reconfigurable architecture are discussed in detail, which includes the implementations of algorithms circuit, register file with controllable node, decoder, interface and main controller. from the introduction of design process of every module circuit, we can see easily some general feature of vlsi design with hdl

    在此基礎上詳細討論了基於可重組體系結構的密碼晶元設計方法和各電路實現的結構圖，包括演算法電路、可控節點寄存器堆、譯碼電路、介面電路和主控模塊電路等。通過對各個模塊設計過程的介紹，闡明了使用hdl語言設計超大規模集成電路的一般特點。
  17. Detail specification for electronic components. semiconductor integrated circuit ct54ls138 ct74ls138 3 - to - 8 line decoder

    電子元器件詳細規范.半導體集成電路ct54ls138 ct74ls138型3線? 8線譯碼器
  18. Bcd detail specification for electronic component. semiconductor integrated circuit - cc4028 cmos 4 - line to 10 - line decoder with bcd - in

    電子元器件詳細規范.半導體集成電路cc4028型cmos 4線? 10線譯碼器
  19. Detail specification for electronic components. semiconductor integrated circuit ct5442 ct7442 4 - line - to - 10 - line decoder bcd - to - decimal

    電子元器件詳細規范.半導體集成電路ct5442 ct7442型4線- 10線譯碼器bcd輸入
  20. In this paper, we aim at the research to the decoding algorithm of turbo product codes, according to the principles of the log - likelihood ratio and the maximum a posteriori criterion, bunt the log - likelihood ratio approximating expression, form the correct strategy of iterative soft decoding, and present the optimal algorithm through software

    幾乎所有tpc的應用研究都集中於採用矩陣交織，軟進/軟出（ siso ） 、重復譯碼的方式上。本文主要是針對tpc譯碼演算法進行研究，依據對數似然概率（ llr ）和最大后驗準則的原理，推導出對數似然概率估算的近似公式，形成tpc重復軟譯碼糾錯演算法，並通過軟體實現。
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