塊寄存器 的英文怎麼說
中文拼音 [kuāijìcúnqì]
塊寄存器
英文
block register-
Firstly, the thesis summarizes the compilation optimizations in modern compiler and the direction of low - power compilation, then analyses the modern compiler such as impact and trimaran, especially their register allocation strategies
本文首先概述了現代編譯器中的編譯優化技術以及低功耗編譯的方向，具體分析了面向指令級優化的編譯器impact和trimaran ，分析了其中的組成模塊，並深入了解其中的寄存器分配機制。This converter includes not only analog parts such as the bandgap voltage reference, voltage pump, sample / hold unit, one bit comparator of high precision, multiply - by - two and difference unit, but also digital parts such as register and multiplexer. so the design of this type of converter is mixed signal design
模數轉換器的內部電路包括基準源、降壓模塊、抽樣保持電路單元、高精度的1bit比較器、倍乘作差單元等模擬電路模塊，以及寄存器組、選擇器等數字電路模塊，屬于數模混合電路。This driver module includes implementation of addressing encoder end ’ s internal register, reading encoded data from the encoder end and the interrupt handler of the encoder end
整個驅動模塊實現了對編碼端內部各寄存器的訪問，從編碼板讀取編碼數據和預覽數據，以及編碼系統中斷處理程序等功能。It presents the verification strategy used in the whole eda design flow of the chip. the simulation on module level ( inc. post - layout ) uses the software event - driven simulator, the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator, for the gate - level netlist produced by using top - down design flow, the sta tool can analyze the static timing, and more formal verification is used to ensure the correct function
本章還提出了系統在整個eda設計流程中的設計驗證策略方法：模塊級的模擬（包括布線后的模擬）全部採用事件驅動式的軟體模擬工具來驗證，各大模塊的聯合模擬及整個晶元的功能驗證（寄存器傳輸級與門級）使用基於周期的模擬工具和硬體模擬器；對于採用top - down的設計方法得到的門級網表使用專門的靜態時序分析工具來進行時序分析以及採用形式驗證來保證正確的功能。The configuration that uses ieee - 13 94 to control a vxi system is introduced. chapter 2 describes the resource manager application of message - based device 13 94 - vxi controller and the mechanism of register - based device arbitrary waveform generator ( awg ). the key technology of interface circuit and direct digital synthesis in awg module is discussed explicitly
本文先對vxi總線技術進行了概略的介紹，在此基礎上，對一具體的vxi寄存器基任意波形發生器模塊進行展開，介紹了任意波形發生器模塊與vxi機箱背板總線通訊的介面電路部分及波形發生機理的核心部分的直接數字合成技術。Rtos - 1750 make use of static memory management to implement memory protection provided by page register ' s memory mapping and bpu ( block protect unit ), with which system keep fast reference as well as relatively independence by the technology of strding - mapping. system manages inner interrupt and outer interrupt by priority classing strategy and provides four type timers, which are system timer, software timer, auxiliary timer and real - time timer
系統充分利用1750a提供的頁面寄存器堆的內存映射功能和塊保護單元（ bpu ）提供的存儲器保護功能，採用靜態內存管理方式，既保證了任務之間的相對獨立，又通過跨段映射技術滿足了dcmpofp中的任務快速引用的要求。In this paper, the methodology and implementation with hdl of design based reconfigurable architecture are discussed in detail, which includes the implementations of algorithms circuit, register file with controllable node, decoder, interface and main controller. from the introduction of design process of every module circuit, we can see easily some general feature of vlsi design with hdl
在此基礎上詳細討論了基於可重組體系結構的密碼晶元設計方法和各電路實現的結構圖，包括演算法電路、可控節點寄存器堆、譯碼電路、介面電路和主控模塊電路等。通過對各個模塊設計過程的介紹，闡明了使用hdl語言設計超大規模集成電路的一般特點。The thread context includes the thread s set of machine registers, the kernel stack, a thread environment block, and a user stack in the address space of the thread s process
線程上下文在線程進程的地址空間內包括線程的一組機器寄存器、核心（ kernel ）堆棧、線程環境塊和用戶堆棧。In the data path, many modules were designed and implemented, such as alu. data bus unit, w ( work register ) and registers file. the designs of peripheral functional modules were finished, including usart, spi and io
在詳細分析riscmcu的體系結構特點的前提下，進行了系統劃分，並詳細設計了該riscmcu的數據通路，包括設計該數據通路上的alu單元、內部數據總線、工作寄存器w以及寄存器文件等功能模塊。A typical calculator chip from rcl semiconductor inc, c9821, is referenced and developed. the chip of the calculator consists of several function units such as rc oscillator, power management module, microprogrammed control unit ( mcu ), register group, lcd driver and keyboard interface
在硬體方面，在完成計算器的功能模塊劃分的基礎上，對包括rc振蕩器、電源模塊、 lcd顯示驅動模塊、鍵盤介面、寄存器組、微程序控制器在內的各個功能模塊的系統結構和電路原理進行了分析，掌握了它們的設計方法。A switch ic for analog signal processing is designed and implemented, which can fulfill the functions of sampling, weighting, controlling and summing of high frequency analog signals. the circuit consists of three parts : four channel analog switches, a voltage reference and the control circuitry. each analog switch is comprised of two high - transconductance n - mosfets with high w / l ratio, which realize the fine tuning and coarse tuning of the input signal respectively
本文研究並設計了一種可對高頻信號進行取樣、加權、控制、疊加的模擬信號處理丌關集成電路，它包括模擬開關、電壓基準源和移位寄存器三個功能模塊，通過兩個高寬長比的高跨導nmos晶體管實現權值的粗調和微調。The vxi versatile plug - in ( vvp ) platform is a register - based, c - size, 32 - bit and single slot instrument. a complete vvp instrument consists of one enhanced main board and four plug - in boards, which is suitable for constructing basic instruments
Vvp系統是一種寄存器基、 c尺寸、單槽位的32位vxi儀器，它採用主板+插板的構架，具體功能分散在若干插板上形成應用子系統，每個主板最多支持4塊插板。This mode uses a shift register that is one block in length and is divided into sections
該模式使用在長度上為一個塊且被分為幾部分的移位寄存器。Finally, the sci module is integrated inside the chip, and reduce the cost of system. besides, there are many programmable registers inside the sci, so it possesses better compatible abilities, it could not only support smart card based on iso7816, but also support smart card base on gsm, emv standards by debuging or updating software
最終設計好的智能卡介面（ sci ）模塊被集成到晶元內部，減少了整機體積和成本，此外， sci內部具有多個可編程寄存器，使得它具有很強的兼容能力，除了支持基於iso7816協議的智能卡外，通過軟體的調試和升級能夠支持包括基於gsm 、 emv等協議的智能卡。A reserved area of memory where the cpu automatically saves the program counter and the contents of working registers when a program interrupt occurs
內存中的一塊留用存儲區，當程序中斷產生時， cpu自動在其中保存程序計數器和工作寄存器的內容。分享友人