譯碼器 的英文怎麼說

中文拼音 [yìmǎqì]
譯碼器 英文
decoder; translator; decipherer; code translator [converter]; matrix gate
  • 譯 : 動詞（翻譯） translate; interpret
  • 碼 : Ⅰ名詞（表示數目的符號或用具） a sign or object indicating number; code Ⅱ量詞1 （指一件事或一類的...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  1. Bcd detail specification for electronic component. semiconductor integrated circuit. type ch2019 4 - line to 10 - line decoder with bcd - in

    電子元器件詳細規范.半導體集成電路ch2019型4線- 10線譯碼器
  2. The interpretation is carried out by the instruction decoder.

    該翻譯借指令譯碼器來進行。
  3. Teleweb - application profile 1 - reference decoder

    遠程.應用范圍.參考譯碼器
  4. Are you struggling through without maude tonight

    今晚沒有譯碼器又讓你頭疼了？
  5. Turbo codes represent the new code structures, which consist of pccc ( parallel serially convolutional code ) and sccc ( serially concatenated convolutional code ). in this paper, the background of turbo codes are firstly introduced, which includes the base principle of error correction code 、 block code and convolutional code ; the principle of turbo code and the iterative decoding is secondly expanded ; the key decoding algorithm : a revised map algorithm and iterative decoding theory are detailed ; then, a new turbo code structure : hccc ( hybrid concatenated convolutional code ) is presented, and the capacity of this code method is analyzed, the average capacity upper bound is derived ; at last, this code is simulated on awgn ( additive white gaussian noise ) channel and rayleigh fading channel

    本文首先介紹了turbo碼的背景知識，包括差錯控制的基本原理、分組碼和卷積碼；然後闡述了turbo碼的基本原理，包括turbo編譯碼器結構及迭代譯碼原理；較為詳細地描述了關鍵的譯碼演算法： ?種改進的最大后驗概率（ map ）譯碼演算法及迭代譯碼演算法；提出了一種新的turbo碼結構：混合turbo碼（混合級聯卷積碼） ；並用編碼性能聯合界分析方法對混合turbo碼進行了性能分析，得出了其平均性能上界；並在高斯白噪聲通道和瑞利衰落通道上分別作了一些應用研究及計算機模擬實驗。
  6. In addition, make out in detail the design on inner combination logic and time logic of fpga, including series - parallel conversion, data selector, counter, flip - latch, timer, encoder, etc. at one time, not only pursuit flow of the data gathering system is illuminated, but also make use of in reason and effectively inner ram resource of fpga and build it in ping - pong framework

    另外，詳細的介紹了fpga內部的組合邏輯和時序邏輯的設計方案，包括串並轉換、數據選擇器、計數器、鎖存器、定時器、譯碼器等。並闡述了數據採集系統的工作流程，而且合理有效地使用了fpga內部的ram資源，將其構建成乒乓式結構。
  7. In the project of constructing the platform, the design of the time - domian synchronization algorithm is in the charge of me, which has been realized on fpga. it is introduced detailedly in chapter 3 and chapter 4. additionally, the design of ldpc decoder based on fpga is another part of the project

    介於本人在該項目中的主要工作是時域同步演算法設計及fpga實現和ldpc碼譯碼器的fpga設計，在文章的第三章將系統的介紹測試平臺時域同步的演算法設計過程及matlab模擬分析，第四章將介紹時域同步的fpga設計、模擬及硬體調試。
  8. The designing process of the edac circuit is described in the paper. the time simulation is analysed, too. the designment of the circuit has access the hardware debug, and can woks normally

    此外還將第一輪設計中的基本邏輯器件如與、或、非門以及諸如244 、 255 、譯碼器等小規模元器件都集成到fpga內部來實現。
  9. The encoder and decoder used in atm switcher are designed using specific error correcting 1c

    設計了atm交換機中編譯碼器模塊。
  10. 5. according to the euclidean algorithm rs encoder and decoder are implemented in fpga

    根據euclid迭代譯碼演算法，用fpga設計實現了rs碼編譯碼器。
  11. In this paper, the common used encoding algorithms and basic finite - field opera - tions algorithms are introduced, and the decoding algorithms such as inverse - free ber - lekamp - massey ( ibm ) algorithm, reformulated inverse - free berlekamp - massey ( ribm ) algorithm and modified euclidean algorithm are analyzed in great detail. based on the ribm algorithm, a modified structure and a pipelined decoder scheme are presented. a tradeoff has been made between the hardware complexities and decoding latency, thus this scheme gains significant improvement in hardware complexity and maximum fre - quency

    本文簡要介紹了有限域基本運算的演算法和常用的rs編碼演算法，詳細分析了改進后的euclid演算法和改進后的bm演算法，針對改進后的bm演算法提出了一種流水線結構的譯碼器實現方案並改進了該演算法的實現結構，在譯碼器復雜度和譯碼延時上作了折衷，降低了譯碼器的復雜度並提高了譯碼器的最高工作頻率。
  12. We mainly improve the calculation of the fano metric on the basis of the original decoding algorithm, which enhance the decoder ’ s speed

    並在原有演算法的基礎上進行了一些改進，主要是針對其fano度量計算的改進，提高了譯碼器的工作速度。
  13. The number of error symbols that can be corrected by the decoder is 2. the design process includes storing the input data, calculating the syndromes, designing multiplier and divider and solving the key equation

    Rs （ 256 ， 252 ）譯碼器的設計過程主要包括輸入數據的存儲、伴隨式的計算、乘法器和除法器的設計、關鍵方程的求解等幾個步驟。
  14. It also discusses the code and decode theory for rs error - correcting codes, then summarizing the design and debug experience for the rs ( 31, 15 ) coder and decoder through fpga

    文章中還討論了rs糾錯碼的編譯碼原理和演算法，總結了基於fpga實現一個rs （ 31 ， 15 ）編碼和譯碼器的設計經驗和調試經驗。
  15. Making logical designs with the integrated decoder

    用集成譯碼器進行邏輯設計
  16. Low power consumption design for viterbi encoder

    譯碼器的低功耗設計
  17. Optimized architectural design of viterbi decoders

    譯碼器的優化設計
  18. Optimized architectural design of viterbi decoder

    譯碼器的優化設計
  19. Low power design methods of setting threshold on viterbi decoder

    譯碼器設置門限的低功耗設計方法
  20. Design of a high - speed viterbi decoder

    高速維特比譯碼器的設計
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