運算計數器 的英文怎麼說

中文拼音 [yùnsuànjìshǔqì]
運算計數器 英文
operation counter
  • 運 : Ⅰ動詞1 （物體位置不斷變化） move; revolve 2 （搬運; 運輸） carry; transport 3 （運用） use; wield...
  • 算 : Ⅰ動詞1 （計算數目） calculate; reckon; compute; figure 2 （計算進去） include; count 3 （謀劃;計...
  • 計 : Ⅰ動詞1 （計算） count; compute; calculate; number 2 （設想; 打算） plan; plot Ⅱ名詞1 （測量或計算...
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 運算 : [數學] operation; arithmetic; operating
  • 計數 : count; tally; counting計數卡 numbered card
  1. Selecting the active run settings the run - settings model that is used with load tests matches the run - configurations model that is used with all test types of team edition for testers

    （可選）在「選定計算機和計數器集將添加到以下運行設置下」之下單擊下箭頭，然後選擇要應用這些計數器集的不同「運行設置」節點。
  2. The key to the fft algorithm is the design of butterfly computation and that of the address logic. the whole schema is designed in the top - down design flow and described in the vhsic hardware description language ( vhdl ), basing on these, we do our research on reconfigurable technology. the result indicates that the data processing ability of reconfigurable system improved greatly

    結果表明，可重構系統在數據處理能力方面比以往的系統有了很大的提高，本設計實現的fft重構處理器可工作於60mhz下，完成一個16點fft需要132個主時鐘周期，完成32點fft需要324個主時鐘周期，而且具有一定可重構性，可以方便地將其運算點數進行擴展，或將其他的圖像處理演算法在實時處理系統中實現。
  3. By using a counter and an operation microprocessor, this paper analyses the measuring method and designs an instrument of edm sinking process in discharge state. this instrument takes samples of voltage, current signal and strong and weak of high frequency signals of detecting voltage amplitude, translates them into various time pulses in discharging state. and a counting unit turns these pulses into digital signals, then send them to a microprocessor. finally various discharge time percentages are sent to the control tache

    通過采樣電火花加工放電間隙的電壓、電流信號和檢測電壓幅值上的高頻信號的強弱，得出反映間隙放電狀態的各種時間脈沖，利用計數器分別對其計數，再送給單片機運算處理，輸出控制環節所需的各種放電狀態時間百分數。
  4. Abstract : by using a counter and an operation microprocessor, this paper analyses the measuring method and designs an instrument of edm sinking process in discharge state. this instrument takes samples of voltage, current signal and strong and weak of high frequency signals of detecting voltage amplitude, translates them into various time pulses in discharging state. and a counting unit turns these pulses into digital signals, then send them to a microprocessor. finally various discharge time percentages are sent to the control tache

    文摘:通過采樣電火花加工放電間隙的電壓、電流信號和檢測電壓幅值上的高頻信號的強弱，得出反映間隙放電狀態的各種時間脈沖，利用計數器分別對其計數，再送給單片機運算處理，輸出控制環節所需的各種放電狀態時間百分數。
  5. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  6. D / a conversion chip and isolation amplifiers are used to obtain the comparative levels required by isolation channels, which could be set with actual requirement ; it can enhance flexibility of the module. otherwise, four - channel isolation signal sources are exported using d / a conversion chip and isolation amplifiers as well

    另外還利用d / a轉換晶元和隔離運算放大器輸出四路隔離信號源，該隔離信號源能與隔離比較電平通過繼電器進行程式控制切換，這樣擴展了該計數器模塊的功能。
  7. Due to the low mechanical efficiency and long circulating period of the down - charging system of cold bed in bar production line, this paper puts forward the improving project, which adopts ethernet supplemented by dp network, applies the fm350 - 2 advanced counter and suitable maths model and combines the technique of the transducer and hydraulic pressure drive control to realize auto - control

    摘要針對棒材生產線上冷床下卸鋼系統機械效率低、運行周期長，不能適應快節奏生產的現狀，採用以工業以太網為主、 dp網為輔的網路通訊，應用西門子fm350 - 2高速計數器，通過有效的數學計算模型，結合變頻器和液壓傳動控制技術，實現網路自動化控制。
  8. The video signal processing circuit realizes the primary catching, filtering and signal amplifying. variable threshold binarization processing circuit and two - channel counter are designed to sample to count the output pulse signal, which is processed, deposited and displayed in microprocessor. the communication interface circuit with the computer is also designed

    視頻信號處理電路完成了原始信號的初級捕捉、濾波、視頻放大等處理，設計了浮動閾值二值化處理電路，採用兩路計數器對輸出脈沖信號采樣計數，最後送入微處理器進行運算處理，可實現測量值的儲存、顯示等，並設計了與上位機的通訊介面。
  9. Digital design ： binary system, boolean algebra, logic gates, simplification of boolean functions, combinational logic. analog design ： amplifiers, frequency response, feedback, operational amplifier

    數位設計：二進位制、布氏代數、邏輯閘、布氏函數的化簡、組合邏輯電路。類比設計：放大器、頻率響應、反饋系統、運算放大器。
  10. Firstly, the system has a good snr and high accuracy, which is owed to wideband operational amplifier being used, accurate adjustment by da, 12 - bit high sampling ad converter being applied. secondly, data transmission becomes less by using forecasting code technology and dictionary compress technology, which are run by dsp on board

    本採集系統採用400mhz增益帶寬積的運算放大器，運用da高精度校準技術，並選用高采樣率低噪聲的12位ad轉換晶元進行模擬電路和ad轉換電路設計，既保證了數據採集系統的信噪比，又提高了系統測量精度。
  11. A counter used in the arithmetical unit to count the steps in multiplication, division, and shift operation

    在運算部件中，對乘、除、移位操作中的操作步進行計數所用的一種計數器。
  12. A register or electric circuit in a calculator or computer, in which the results of arithmetical and logical operations are formed

    在運算部件中，對乘、除、移位操作中的操作步進行計數所用的一種計數器。
  13. The precision amplifier and sixteen bit analog / digital ( a / d ) convertor ad7677 are used in designing data collection module which can convert range automatically

    選用高性能運算放大器及16位模數轉換器ad7677完成了帶有自動量程轉換的數據採集模塊的設計。
  14. And the ways to optimize the circuit architecture, minimize the circuit nonidealities and improve the circuit performance are analyzed combined with the characteristics of the modulator architecture. based on it, the switched - capacitor integrator, class a amplifier, nonoverlap clock, voltage reference, comparator, feedback dac have been designed. in the end, the layout design is shown

    調制器採用全差分開關電容電路實現，並根據系統結構特點就如何優化電路結構、克服電路中存在的非理想特性、提高電路性能作了具體分析，在此基礎上完成了開關電容積分器（開關、電容、運算放大器） 、參考電壓源、比較器、兩相非交疊時鐘、反饋dac等模塊的電路結構和參數設計。
  15. To ensure the precision of distance measuring, the high - speed laser driving circuit and the detect - amplifying circuit constituted by two class high - speed operational amplifiers are used in auto adaptive cruise - control system, and the laser flying time is measured by a sixteen bit ' s binary counter, whose counting frequency is 100 megahertz

    為保障測距精度，裝置採用高速激光器驅動電路和由兩級高速運算放大器構成的探測放大電路，並用一個計數脈沖頻率為100mhz的16位二進制計數器完成激光收發間隔時間的測量。
  16. Advanced fpga technology is introduced to improve the integration of digital circuits, and all digital circuits in the original module are integrated in the fpga chips, which could not only reduce the cost, but also improve the reliability and measurement precision of the circuits. high speed digital signal processor ( dsp ) is selected as the coprocessor instead of scm ; it can receive all kinds of commands sent from vxi, analyze and execute the commands, harmonize each section of the module and process the data. higher - conversion - speed comparator chip is adopted to convert the input signals being measured into square waveform signals which could be identified by fpga chip ; it can expand the measurement range of frequency dramatically

    本文在原有vxi總線四通道計數器模塊的設計基礎上，通過對原模塊缺陷的分析，採用一些新的技術和新的電子器件來重新設計該計數器模塊:採用最新的fpga技術來提高數字電路的集成度，將原模塊中的所有數字電路全部集成在fpga晶元中，這樣不僅能節約成本，還能提高電路的可靠性和測量精度;採用高速的數字信號處理器（ dsp ）取代原有的單片機作為協處理器，來接收vxi發來的各種命令，分析命令、執行命令、協調模塊各部分的工作以及對數據的處理;採用轉換速率更高的比較器晶元將輸入的被測信號轉換為fpga晶元能夠識別的方波信號，能極大提高測量頻率的范圍;採用d / a轉換晶元和隔離運算放大器得到隔離通道所需的比較電平，該比較電平值能夠根據實際需求進行設置，能增強模塊的使用靈活性。
  17. In chapter 3, the configuration of an operational amplifier is confirmed in base of the characteristic parameter, which is needed firstly, and the probable value of configuration parameter in this circuit is calculated artificially

    第三章根據所要求的性能參數確定出運算放大器的結構以及手工算出電路結構參數的大概值。第四章用電路模擬軟體對第三章設計的運算放大器進行模擬分析，細調設計使之優化。
  18. Computes the calculated value of a raw counter sample

    對原始計數器樣本的計算所得值進行運算。
  19. Contains the computed value of a performance counter collected during a load test run

    包含負載測試運行期間收集的性能計數器的計算值。
  20. In the seventh chapter, some of the above proposed new circuit, such as high frequency, high definition 12 - bit, 80mhz samples / s current - steering dac and fully differential r - mosfet - c bessel filter with accurate group delay, high accuracy bandgap reference and high drive capability cmos operational amplifier have been applied in communication gsm baseband i / o port integrated circuit, all the above blocks meet well with the design requirements of the system, and gain the better testing results, in the mean time, the above proposed high accuracy bandgap reference circuit als

    第七章:將本文第二章提出的高速、高精度12位、 80mhz采樣率電流舵結構的數模轉換器和第五章提出的r一mosfet一c結構且具有精確群時延值的貝塞爾（ bessel ）濾波器以及第六章提出的高精度帶隙基準電壓源和高驅動能力全差分運算放大器電路應用於通信gsm基帶輸入/輸出埠晶元，滿足系統設計要求並取得了令人滿意的實測結果。
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